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LDS285 data sheet 720 source (240 x rgb) + 320 gate 16m-color one-chi p tft driver preliminary feb. 27, 2007 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 confidential leadis technology version 2.00 contents 1 description 2 2 features 2 3 block diagram 4 4 pin description 5 5 functional description 10 5.1 mpu interface .................................................................................................................. .................... 10 5.1.1 interface type selection ....................................................................................................... ........................... 10 5.1.2 general protocol ............................................................................................................... ............................... 11 5.1.3 8080-series parallel interface (p68 = "l")..................................................................................... .................. 12 5.1.4 6800-series parallel interface (p68 = "h") ..................................................................................... ................. 15 5.1.5 serial interface ............................................................................................................... .................................. 18 5.1.6 interface pause................................................................................................................ ................................ 22 5.1.7 data transfer recovery......................................................................................................... .......................... 23 5.1.8 display module data transfer modes ............................................................................................. ................ 25 5.2 display data ram (ddram)....................................................................................................... ......... 26 5.2.1 display data formats ........................................................................................................... ........................... 27 5.2.2 rgb interface .................................................................................................................. ................................ 41 5.2.3 address counter ................................................................................................................ .............................. 49 5.2.4 memory map ..................................................................................................................... ............................... 51 5.2.5 normal display on or partial mode on ........................................................................................... ................ 52 5.2.6 tearing effect output line..................................................................................................... .......................... 53 5.3 instruction decoder & register ................................................................................................ 5 7 5.4 system clock generator ......................................................................................................... ...... 57 5.5 oscillator..................................................................................................................... ........................ 57 5.6 source driver ....... ........................................................................................................... ................... 57 5.7 gate driver .................................................................................................................... ....................... 58 5.8 rgb interface timing diagram ................................................................................................... ... 59 5.8.1 relationship between input signal and output signal (rgb i/ f mode 3) ...................................................... 59 5.8.2 input / output timing chart (g0->g320, s1->s720)............ ................................................................... ........ 60 5.9 lcd power generation circuit................................................................................................... .. 61 5.9.1 lcd power generation scheme ........................................ ............................................................ ................. 61 5.9.2 various boosting steps ......................................................................................................... .......................... 62 5.9.3 gray voltage generator......................................................................................................... .......................... 63 5.9.4 temperature compensation ....................................................................................................... ..................... 70 5.10 power on/off sequence.......................................................................................................... ........ 71 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 confidential leadis technology version 2.00 5.10.1 case 1 ? resb line is held high or unstable by host at po wer on............................................................... 7 1 5.10.2 case 2 ? resb line is held low by host at power on ....... ...................................................................... ....... 72 5.11 uncontrolled power off ......................................................................................................... ..... 72 5.12 power flow chart for different power modes ................................................................. 73 5.13 input / output pin state ....................................................................................................... ............ 74 5.13.1 output or bi-directional (i/o) pins............................................................................................ ........................ 74 5.13.2 input pins ..................................................................................................................... .................................... 74 5.14 sleep out ?command and self-diagnostic functions of the display module ........ 75 5.14.1 register loading detection..................................................................................................... .......................... 75 5.14.2 functionality detection ........................................................................................................ ............................ 76 5.14.3 chip attachment detection (optional)............................. .............................................................. ................... 77 5.14.4 display glass break detection (optional) ....................... ................................................................ ................. 78 6 adaptive bcaklight control and led driver control 79 6.1 labc ( light adaptive backlight control) ............................................................................... 79 6.1.1 system block diagam with als (ambient light sensor) and LDS285........................................................... 79 6.1.2 labc function flow ............................................................................................................. ........................... 80 6.2 cabc ( content adaptive backlight control) ........................................................................ 82 6.2.1 cabc function flow............................................................................................................. ........................... 83 6.3 cabc and labc ................................................................................................................. .................... 83 6.4 led driver control ............................................................................................................. .............. 84 6.4.1 led driver control with pwm pulse ............................... ............................................................... .................. 84 6.4.2 led driver control with 1-wire digital interface( only for ld s8861 ) ........................................................... .... 86 7 instruction description 88 7.1 instruction code ............................................................................................................... ................ 88 7.1.1 instruction code table......................................................................................................... ............................ 88 7.1.2 no (00h) ....................................................................................................................... ................................... 92 7.1.3 swreset: software reset (01h) .................................................................................................. ................. 93 7.1.4 rddid: read display id (04h) ................................................................................................... ..................... 94 7.1.5 rddst: read display status (09h) ............................................................................................... ................. 95 7.1.6 rddpm: read display power mode (0ah) ........................................................................................... .......... 97 7.1.7 rddmadctr: read display madctr (0bh)........................................................................................... ..... 98 7.1.8 rddcolmod: read display pixel format (0ch) .................... ................................................................. ..... 99 7.1.9 rddim: read display image mode (0dh) ........................... ................................................................ ......... 100 7.1.10 rddsm: read display signal mode (0eh) .......................................................................................... ......... 101 7.1.11 rddsdr: read display self-diagnostic result (0fh) ......... ..................................................................... ... 102 7.1.12 slpin: sleep in (10h) .......................................................................................................... .......................... 103 7.1.13 slpout: sleep out (11h) ........................................................................................................ ..................... 105 7.1.14 ptlon: partial display mode on (12h) ............................. .............................................................. ............. 107 7.1.15 noron: normal display mode on (13h)............................................................................................ .......... 108 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 confidential leadis technology version 2.00 7.1.16 invoff: display inversion off (20h).............................. .............................................................. ................. 109 7.1.17 invon: display inversion on (21h)................................ .............................................................. ................. 110 7.1.18 gamset: gamma set (26h) ........................................................................................................ ................. 111 7.1.19 dispoff: display off (28h) ..................................................................................................... ..................... 112 7.1.20 dispon: display on (29h) ....................................................................................................... ..................... 113 7.1.21 caset: column address set (2ah)................................. ............................................................... .............. 114 7.1.22 raset: row address set (2bh) ................................................................................................... ................ 116 7.1.23 ramwr: memory write (2ch) ...................................................................................................... ................ 118 7.1.24 ramrd: memory read (2eh) ....................................................................................................... ................ 119 7.1.25 ptlar: partial area (30h) ...................................................................................................... ....................... 120 7.1.26 teoff: tearing effect line off (34h) ........................................................................................... .............. 122 7.1.27 teon: tearing effect line on (35h)............................................................................................. ................ 123 7.1.28 madctr: memory data access control (36h).................... ................................................................... ...... 124 7.1.29 idmoff: idle mode off (38h) .................................................................................................... .................... 126 7.1.30 idmon: idle mode on (39h)...................................................................................................... .................... 127 7.1.31 colmod: interface pixel format (3ah)........................................................................................... ............. 129 7.1.32 wrdisbv : write display brightness (51h) ....................... ................................................................ ........... 130 7.1.33 rddisbv : read display brightness (52h)........................................................................................ ........... 131 7.1.34 wrctrld: write ctrl display (53h).............................................................................................. ............ 132 7.1.35 rdctrld : read ctrl value disp lay (54h)........................................................................................ ....... 133 7.1.36 wrcabc: write content adaptive brightness (55h) ................................................................................ .... 134 7.1.37 rdcabc : read content adaptive brightness (56h) ............... ................................................................. ... 135 7.1.38 rdid1: read id1 value (dah) .................................................................................................... .................. 136 7.1.39 rdid2: read id2 value (dbh) .................................................................................................... .................. 137 7.1.40 rdid3: read id3 value (dch) .................................................................................................... .................. 138 7.1.41 ifmode: set display interface mode (b0h) .................... ................................................................... .......... 139 7.1.42 disclk: display clock set (b1h)................................................................................................ .................. 141 7.1.43 invctr: inversion control (b2h) ................................................................................................ .................. 143 7.1.44 regctr: regulator control (c0h) ................................................................................................ ............... 145 7.1.45 vcomctr: vcoml / vcomh voltage control (c1h) ................... .............................................................. 14 6 7.1.46 gamctr1: set gamma correction characteristics (c8h) ............. .............................................................. 1 47 7.1.47 gamctr2: set gamma correction characteristics (c9h) ............. .............................................................. 1 48 7.1.48 gamctr3: set gamma correction characteristics (cah)............. .............................................................. 1 49 7.1.49 gamctr4: set gamma correction characteristics (cbh)............. .............................................................. 1 50 7.1.50 eppgmdb: write id2, vcom offset value .......................................................................................... ........ 151 7.1.51 eperase: eprom erase (d1h) ..................................................................................................... ............. 154 7.1.52 epprog: eprom program (d2h) .................................................................................................... ........... 155 7.1.53 eprdvrf: eprom read verify (d3h) ............................................................................................... ......... 156 7.1.54 rdvcof: vcom offset registers bits read back (d9h) .......... ................................................................... .157 7.1.55 ledctrl: write the configuration for led driver.............. .................................................................. ......... 158 7.2 reset table (default value) (tbd) ............................................................................................. 1 60 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 confidential leadis technology version 2.00 7.3 instruction setup flow ......................................................................................................... ....... 161 7.3.1 initializing with the built-in power supply circuits (tbd ) ..................................................................... ......... 161 7.3.2 power off sequence (tbd)....................................................................................................... .................. 162 7.3.3 eeprom access sequence for initialization (data clear) ......... ................................................................ .. 163 7.3.4 eeprom access sequence for program (data write) (tbd) ......... .............................................................. 164 8 specifications 165 8.1 absolute maximum ratings ....................................................................................................... ... 165 8.2 esd protection l evel ...... ..................................................................................................... .......... 165 8.3 latch-up protection level ...................................................................................................... .... 165 8.4 light sensitivity.............................................................................................................. .................. 165 8.5 maximum series resistance ...................................................................................................... ... 166 8.6 dc characteristics ............................................................................................................. ............ 167 8.6.1 basic characteristics .......................................................................................................... ........................... 167 8.6.2 current consumption............................................................................................................ ......................... 169 8.7 ac characteristics(tbd)........................................................................................................ ........ 170 8.7.1 parallel interface characteristics (8080-series mpu) ...... ..................................................................... ........ 170 8.7.2 parallel interface characteristics (6800-series mpu) ...... ..................................................................... ........ 172 8.7.3 serial interface characteristics (3-pin serial) ............ .................................................................... ............... 174 8.7.4 serial interface characteristics (4-pin serial) ............ .................................................................... ............... 175 8.7.5 rgb interface characteristics ........................................ .......................................................... ..................... 177 8.7.6 reset input timing............................................................................................................. ............................ 178 8.7.7 measurement conditions......................................................................................................... ...................... 179 9 reference applications 183 9.1 microprocessor interface....................................................................................................... .. 183 9.1.1 interfacing with 3-pin serial mode (p68 = "l", bs2=?l?, bs1 = "l", bs0 = "l") ........................................... 183 9.1.2 interfacing with 4-pin serial mode (p68 = "h", bs2=?l?, bs1 = "l", bs0 = "l")........................................... 183 9.1.3 interfacing with 8080-series mpu 8-bit bus (p68 = "l", bs2 =?l?, bs1 = "l", bs0 = "h")............................ 184 9.1.4 interfacing with 6800-series mpu 8-bit bus (p68 = "h", bs 2=?l?, bs1 = "l", bs0 = "h") ........................... 184 9.1.5 interfacing with 8080-series mpu 9-bit bus (p68 = "l", bs2 =?h?, bs1 = "l", bs0 = "l")............................ 185 9.1.6 interfacing with 6800-series mpu 9-bit bus (p68 = "h", bs 2=?h?, bs1 = "l", bs0 = "l") ........................... 185 9.1.7 interfacing with 8080-series mpu 16-bit bus (p68 = "l", bs 2=?l?, bs1 = "h", bs0 = "h") ......................... 186 9.1.8 interfacing with 6800-series mpu 16-bit bus (p68 = "h", bs2 =?l?, bs1 = "h", bs0 = "h") ........................ 186 9.1.9 interfacing with 8080-series mpu 18-bit bus (p68 = "l", bs 2=?h?, bs1 = "h", bs0 = "l") ......................... 187 9.1.10 interfacing with 6800-series mpu 18-bit bus (p68 = "h", bs2 =?h?, bs1 = "h", bs0 = "l") ........................ 187 9.2 connections with lcd panel ..................................................................................................... .. 188 9.2.1 one layer connection for gate output........................................................................................... ............... 188 9.2.2 two layer connection for gate output............................... ............................................................ ............... 189 9.3 example connection with pan el (case11) ..... ......................................................................... 190 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 confidential leadis technology version 2.00 9.4 connection example with external components ............................................................. 191 9.4.1 application circuit example .................................................................................................... ....................... 192 9.5 external components connection.......................................................................................... 193 10 chip information 194 10.1 chip overview .................................................................................................................. .................. 194 10.2 bump information............................................................................................................... .............. 196 10.2.1 source / gate / vcom / gate control / output side dummy p ad format ..................................................... 196 10.2.2 input / input side dummy pad format .............................. .............................................................. ............... 197 10.3 pad coordinates................................................................................................................ ............... 198 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 1 confidential leadis technology document no: ltt285a-000 prepared by: sam_oh revision history date contents version oct. 17, 2006 - preliminary version 0.00. ver. 0.00 (preliminary) feb. 1, 2007 totally revised ver. 1.00 (preliminary) mar. 1, 2007 command , eeprom and dbc description ver. 2.00 (preliminary) www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 2 confidential leadis technology 1 description LDS285 is a single chip low power cmos lcd controller/driver for color tft-lcd displays of 320 gates and 240xrgb columns. it has a 1.84m-bit (240 x 24bit x 320) display ram and a full set of control functions. LDS285 offers 10 kinds microprocessor interfaces: 8080-system (8-bit, 9-bit, 16-bit, 18-bit), 6800-system (8-bit, 9-bit, 16-bit, 18-bit) and serial (3-pin or 4-pin). it also supplies 24-bit or 8-bit rgb interface for driving video signal directly from controller. 2 features ? single chip tft-lcd controller/driver ? outputs: - 720 source outputs (240 x rgb) - 320 gate outputs - common electrode output ? display mode (color modes): - full colors (idle mode off): 16m-colors,262k-colors - reduced color (idle mode on): 8-colors (3-bit binary mode) ? interface mode (color modes on the display host interface): - 24 bit/pixel: (rgb) = (888) using the 1.84m-bit frame memory directly - 18 bit/pixel: (rgb) = (666) using the 1.84m-bit frame memory with 256k-colors ? display data ram (ddram): 240 x 320 x 24-bit = 1.84m bit ? mpu interfaces: - 3-pin or 4-pin serial interface - 8-bit, 9-bit, 16-bit, 18-bit interface with 8080-series mpu - 8-bit, 9-bit, 16-bit, 18-bit interface with 6800-series mpu - 24-bit or 8-bit rgb interface with graphic controller ? display features - partial display mode - software programmable color depth mode - n-line inversion for low cross talk ? on chip: - dc/dc converter - adjusted vcom generation by mtp - oscillator for display clock generation. - one set of 4 gamma curves with micro-adjustment points - temperature compensation for display quality ? driving algorithm: - line inversion, frame inversion www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 3 confidential leadis technology ? i/o supply voltage range. 1.65 to 3.3v ? optional logic supply voltage range vdd1 to vss1 (when psel=low): 1.65 to 1.95v vdd1 to vss1 (when psel=high): 1.95 to vdd2 ? analog supply voltage range vdd2 to vss2: 2.3 to 3.3v ? output voltage levels: - source output voltage range vs to vss2: 3.0 to 6.0 v - common electrode output voltage range vcom amplitude (max) = 5.5v - vcomh output voltage range vcomh to vss2 2.0 to 5.0v - vcoml output voltage range vcoml to vss2 -2.0 to 1.0v - positive gate output voltage range: +12.0 to +16.0 v when vr=4 - negative gate output voltage range: -8.0 to ?12.0 v when vr=4 ? low power consumption, suitable for battery operated systems ? cmos compatible inputs ? optimized layout for cog assembly ? temperature range: -30 ~ 70 c (to +85 c no damage) ? support dbc(dynamic backlight control) function and als(ambient light sensing )function ? support normal black / normal white lcd ? support wide view angle display www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 4 confidential leadis technology 3 block diagram vcomh vcom vcoml c6p c6m vcl c5p c5m c4p c4m c3p c3m vgh vgl c2p c2m c1p c1m avdd vreg_dc padb0 to padb4 pada0 to pada4 vdc1 vdd2 vdd2_dc vss2, vss2_dc vdd1,vdd1_r vdd1_io vss1, vss1_r tgs, frm , psel test1, test4 test2, test3 te osc me_cmp smx, smy srgb, sinv, extc led_cnt p68 bs2, bs1, bs0 resb csb rdb wrb(d!c) dc(scl) d23 to d0(sda) mpu i/f & data latch (3-/4-pin serial, 8/9/16/18 bit parallel & 24-bit rgb) instruction control system clock generator display data ddram 240 x 320 x 24 = 1,843,200 bits ddram data generator row address counter scan address counter column address counter data latch 720 source buffer 320 gate buffer tft-lcd panel (16m-color) g1 g320 oscillator mtp fpc cap cap connect capacitors mpu interface bias vcom generator booster3 booster2 booster1 gate counter d/a converter level shifter level shifter vs vr vd0 vsync hsync dck enable vsynco gamma generator vs vr vref vr s1 - ---------s720 rgb i/f vreg_dc www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 5 confidential leadis technology 4 pin description table 4.1.1 pin description name type description driver output pins s1 to s720 o source driver output pins. g1 to g320 o gate driver output pins. power supply pins psel i i/o power voltage level selection pin. when psel=?vss2? : i/o signal voltage should be less than 1.95v and in this case, vdd1_io and vdd1 should be connected together and external power for i/o system should be supplied to those pins ( vdd1_io and vdd1) when psel=?vdd2? : i/o signal voltage should be larger than 1.95v and in this case, vdd1_io and vdd1 should not be connected together and external power for i/o system should be supplied to vdd1 _io and vdd1 should have stabilization capacitor (about 2.2uf) to vss. vdd1_io p power supply for i/o circuit system. (refer psel pin description) vdd1, vdd1_r p power supply for logic system. (refer psel pin description) vdd2, vdd2_dc p power supply for analog system and boosting input voltage. 2.3v~3.3v supported. all vdd2 and vdd2_dc pins must be externally connected. vss1, vss1_r, vss2 vss2_dc p system ground for logic and analog circuits. all vss1,vss1_r and vss2,vss2_dc pins must be externally connected to system ground. d_vdd1o po dummy vdd1_io power output pin. it can be used to fix some input pins to ?h ? level and must be left open if not used. d_vss1 po dummy vss1 power output pin. it can be used to fix some input pins to ?l ? level and must be left open if not used. me_cmp p macro eeprom write - erase power. when you write on internal eeprom you must provide power through this pin and it must be left open when you do not write on eeprom. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 6 confidential leadis technology pin description (continued) name type description lcd supply voltage generation (dc-dc converter and regulator) c1p to c6p, c1m to c6m i/o capacitor connection pins for booster circuits. avdd o output of booster circuit (2*vdd2 or 3*vreg_dc). connect capacitor to vss (gnd) vdc1 i 1 st booster reference voltage using vs<4.2v , vdc1 and vdd2_dc should be connected together using vs>4.2v , vdc1 and vreg_dc should be connected together vreg_dc o output of the vreg_dc regulator connect capacitor between vreg_dc and system ground (gnd). using vs>4.2v , vdc1 and vreg_dc should be connected together vr o output of the vr regulator. connect capacitor between vr and system ground (gnd). vs o output of the vs regulator. all vs pads in left side and right side must be connected together by external metal layer for lower resistance. connect stabilizing capacitor betwee n vs and system ground (gnd). vgh o positive reference voltage for gate driver circuits (3*vr or 4*vr). please refer to the 5.9.2 various boosting steps for details vgl o negative reference voltage for gate driver circuits (-2*vr or -3*vr). please refer to the 5.9.2 various boosting steps for details vcl o negative voltage output of booster circuits for vcom (-1*vdd2) vcomh o positive voltage output of vcom. vcoml o negative voltage output of vcom. vcom o common output signal. the swing voltage level is vcoml to vcomh. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 7 confidential leadis technology pin description (continued) name type description host interface pins p68,bs2,bs1, bs0 i interface mode setting (please refer to the section 5.1). in the serial interface mode, rgb interface mode can be used by ?enable? pin. resb i this signal will reset the device and must be applied to properly initialize the chip. signal is active low. csb (!sce) i chip select input pin (?low? enable). th is pin can be permanently fixed ?low? in parallel interface mode only. if csb is connected to ground in parallel interface mode, there will be no abnormal visible effect to the display module. also there will be no restriction on using the parallel read/write protocols, power on/off sequences or other functions. furthermore there will be no influence to the power consumption of the display module. d/!c(scl) i display data / command selection pin in parallel interface. in serial i/f, this is used scl. if not used, please connect to ground or vdd1_io this pin. wrb (rw) (d/!c) i write enable in 8080-series parallel interface. read write selection in 6800-series parallel interface. in serial i/f, this is used d/!c for 4-line serial. if not used, please connect to ground or vdd1_io this pin. rdb (e) i read enable in 8080-series parallel interface. read/write enable in 6800- series parallel interface. if not used, please connect to ground or vdd1_io this pin. te o tearing effect output. if not used, please open this pin. d23to d8, d7 to d0 i/o 18-bit bi-directional display data bu s for parallel interface with mpu. 16-bit bi-directional display data bu s for parallel interface with mpu. 9-bit bi-directional display data bus for 9-bit parallel interface. 8-bit bi-directional display data bus for 8-bit parallel interface. 8-bit command bus for 18-bit, 16-bit, 9-bit and 8-bit parallel interface. in 8-bit parallel, d7 to d0 are used and the others (d23 to d8) should be connected to vss1. in 9-bit parallel, d8 to d0 are used and the others (d23 to d9) should be connected to vss1. in 16-bit parallel, d23 to d16 are not used and should be connected to vss1. in 18-bit parallel, d23 to d18 are not used and should be connected to vss1. in serial interface, d23 to d1 are not used and should be let open or connected to vss1. in only rgb interface, d23 to d18 are used. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 8 confidential leadis technology pin description (continued) name type description mode select srgb i module rgb order select pin. (refer section 8.2) sinv i source output data polarity select pin. (sinv=h: data reverse) (refer section 8.2) smx i module source output direction select pin. (refer section 8.2) smy i module gate output direction select pin. (refer section 8.2) extc i enable pin for extended command set and test command set. to use extended command set and test command set (such as eeprom write), please connect this pin to vdd1_io. during normal operation, please open this pin. (internal rpull-down=15k ) tgs i enable pin for extended command set. to use extended command and normal command sets only, please connect this to vss1 and make extc connected to vss1 or open. ( the test commands can not be used and are treated as nops). to use normal command set only, please connect this to vdd1 and open extc. led_control led_cnt o back-light control output. if not used, please open this pin www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 9 confidential leadis technology pin description (continued) name type description clock input and rgb interface osc i oscillator input for test purpose. if not used, please connect this pin to vss1 vsync i vertical sync input for rgb interface. it used as a start pulse input for the gate driver circuits. if not used, please connect this pin to vss1. hsync i horizontal sync input for rgb interface. it used as a start pulse input to receive the valid data for the source driver circuits. if not used, please connect this pin to vss1. dck i pixel data clock input for rgb interface. when the rgb interface is used, the dot clock is input. the rgb data of vd17 to vd0 pins are read at the rising edge or falling edge of this signal. if not used, please connect this pin to vss1. enable i rgb interface enable pin. this pin is used for the rgb data enable signal when rgb interface is used. if not used, please connect this pin to vss1. vd0 i lsb of rgb interface data bus. since d23~d1 are shared between rgb interface and parallel interface, only vd0 is used. if not used, please connect these pins to vss1. vsynco o rgb interface vertical sync output for rgb interface. if not used, please open this pin. test pins pada0 padb0 i pins for display glass break detection. refer to the section 5.14.4 for details. if not used, please open these pins. pada1 to pada4 padb1 to padb4 i pins for chip attachment detection. refer to the section 5.14.3 for details. if not used, please open these pins. frm i test input pin. free running mode test. you can use this pin when you do reliability test for your panel. if not used, please open this pin (internal rpull-down=15k ). test1 o test pin, not accessible to user must be left open. test2 i test pin, not accessible to user must be left open. test3 i test pin, not accessible to user must be left open. test4 o test pin, not accessible to user must be left open. dummy - dummy pins. these pins can be used for ito routing. note: dummy ? these pins should be open (float). www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 10 confidential leadis technology 5 functional description 5.1 mpu interface LDS285 can interface with mpu at high speed. however, if the interface cycle time is faster than the limit, mpu needs to have dummy wait(s) to meet the cycle time limit. 5.1.1 interface type selection the selection of a given interfaces are done by setting p68, bs2, bs1 and bs0 pins as shown in table 5.1.1 and table 5.1.2. table 5.1.1 interface type selection p68 bs1 bs1 bs0 interface read back select 0 0 0 0 3-pin serial interface via the read instruction (8-bit, 24-bit and 32-bit read parameter) 0 0 0 1 8080 mpu 8-bit parallel rdb strobe (8-bit read data and 8-bit read parameter) 0 0 1 1 8080 mpu 16-bit parallel rdb strobe (16-bit read data and 16-bit read parameter) 0 1 0 0 8080 mpu 9-bit parallel rdb strobe (9-bit read data and 8-bit read parameter) 0 1 1 0 8080 mpu 18-bit parallel rdb strobe (18-bit read data and 16-bit read parameter) 1 0 0 0 4-pin serial interface via the read instruction (8-bit, 24-bit and 32-bit read parameter) 1 0 0 1 6800 mpu 8-bit parallel e strobe (8-bit read data and 8-bit read parameter) 1 0 1 1 6800 mpu 16-bit parallel e strobe (16-bit read data and 16-bit read parameter) 1 1 0 0 6800 mpu 9-bit parallel e strobe (9-bit read data and 8-bit read parameter) 1 1 1 0 6800 mpu 18-bit parallel e strobe (18-bit read data and 16-bit read parameter) table 5.1.2 pin connection according to the interface type p68 bs2 bs1 bs0 interface rdb wrb dc d23-d0 0 0 0 0 3-pin serial interface *1) *1) scl *1) d23-d1: unused, d0: sda 0 0 0 1 8080 mpu 8-bit parallel rdb wrb dc *1) d23-d8: unused, d7-d0: 8-bit data 0 0 1 1 8080 mpu 16-bit parallel rdb wrb dc *1) d23-d16: unused, d15-d0: 16-bit data 0 1 0 0 8080 mpu 9-bit parallel rdb wrb dc *1) d23-d9: unused, d8-d0: 9-bit data 0 1 1 0 8080 mpu 18-bit parallel rdb wrb dc *1) d23-d18: unused, d17-d0: 18-bit data 1 0 0 0 4-pin serial interface *1) dc scl *1) d23-d1: unused, d0: sda 1 0 0 1 6800 mpu 8-bit parallel e rw dc *1) d23-d8: unused, d7-d0: 8-bit data 1 0 1 1 6800 mpu 16-bit parallel e rw dc *1) d23-d16: unused, d15-d0: 16-bit data 1 1 0 0 6800 mpu 9-bit parallel e rw dc *1) d23-d9: unused, d8-d0: 9-bit data 1 1 1 0 6800 mpu 18-bit parallel e rw dc *1) d23-d18: unused, d17-d0: 18-bit data note: 1) unused pins can be open, connected to vss1 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 11 confidential leadis technology 5.1.2 general protocol for programming of the lcd driver, the general supported protocol is shown in fig. 5.1.1 s: start data tranamission p: stop data tranamission tb: tranamission byte tb tb tb tb tb tb s p fig. 5.1.1 programming protocol if data write or parameter write is interrupted by any other command, data write command or parameter write command should be done again to write the remained data or parameter. cmd1 command1 code (with 3 parameter) para11 para12 para13 cmd1 para11 para12 para13 cmd2 para11 cmd1 command1 code is interrupped by command2 command1 with 1 s t parameter (para11) should be executed again to write remained paramete r (para12 and para13) fig. 5.1.2 write interrupt sequence www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 12 confidential leadis technology 5.1.3 8080-series parallel interface (p68 = "l") the 8080-series bi-directional interface can be used for communication between the micro controller and the lcd driver chip. the selection of this interface is done when p68 pin is ?l? state (vss1). interface bus width can be selected with bs2, bs1 and bs0. the interface functions of the parallel interface (8080-series) are given in table 5.1.3. table 5.1.3 parallel interface function (8080-series, p68=?l?) 8080-series bs2 bs1 bs0 interface dc rdb wrb function 1 1 write 8-bit display data or 8-bit parameter (d7 to d0) 0 1 write 8-bit command (d7 to d0) 1 1 read 8-bit display data (d7 to d0) 0 0 1 8-bit interface 1 1 *1) read 8-bit parameter or status (d7 to d0) 1 1 write 16-bit display data (d15 to d0) or 8-bit parameter (d7 to d0) 0 1 write 8-bit command (d7 to d0) 1 1 read 16-bit display data (d15 to d0) 0 1 1 16-bit interface 1 1 *1) read 8-bit parameter or status (d7 to d0) 1 1 write 9-bit display data(d8 to d0) or 8-bit parameter (d7 to d0) 0 1 write 8-bit command (d7 to d0) 1 1 read 9-bit display data (d8 to d0) 1 0 0 9-bit interface 1 1 *1) read 8-bit parameter or status (d7 to d0) 1 1 write 18-bit display data (d17 to d0) or 8-bit parameter (d7 to d0) 0 1 write 8-bit command (d7 to d0) 1 1 read 18-bit display data (d17 to d0) 1 1 0 18-bit interface 1 1 *1) read 8-bit parameter or status (d7 to d0) note: ? ? = rising edge *1) applied for command code: dah, dbh, dch, 0ah, 0bh, 0ch, 0dh, 0eh, 0fh, 04h and 09h www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 13 confidential leadis technology the parallel interface timing diagram is given in fig. 5.1.3 and fig. 5.1.4. cmd pa 1 cmd pa n-2 pa n-1 cmd csb dc rdb wrb d[k:0] host d[k:0] (mpu to lcd) driver d[k:0] (lcd to mpu) 1-byte command 2-byte command n-byte command (number of parameter = n-1) s p cmd pa 1 cmd pa n-2 pa n-1 cmd cmd: write command code pa: write parameter or ram data [k:0] : k means the used data bus. refer to table 5.1.3 signals on d[k:0], dc, rdb and wrb pins during csb=?h? are ignored. cmd pa 1 cmd pa n-2 pa n-1 cmd hi-z pa 1 pa 1 pa 1 fig. 5.1.3 8080-series parallel bus protocol, write to register or display ddram www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 14 confidential leadis technology dm pa cmd data cmd read parameter read display ram data s p csb dc rdb wrb d[k:0] host d[k:0] (mpu to lcd) driver d[k:0] (lcd to mpu) dm data signals on d[k:0], dc, rdb and wrb pins during csb=?h? are ignored. dm cmd cmd pa dm pa pa hi-z cmd cmd hi-z dm pa dm pa pa hi-z hi-z hi-z hi-z cmd: write command code pa: write parameter or ram data [k:0] : k means the used data bus. refer to table 5.1.3 fig. 5.1.4 8080-series parallel bus protocol, read from register www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 15 confidential leadis technology 5.1.4 6800-series parallel interface (p68 = "h") the 6800-series bi-directional interface can be used for communication between the micro controller and the lcd driver chip. the selection of this interface is done when p68 pin is ?h? state (vdd1_io). interface bus width can be selected with bs2, bs1 and bs0. the interface functions of the parallel interface (6800-series) are given in table 5.1.4. table 5.1.4 parallel interface function (6800-series, p68=?h?) 6800-series bs2 bs1 bs0 interface dc rw e function 1 0 write 8-bit display data or 8-bit parameter (d7 to d0) 0 0 write 8-bit command (d7 to d0) 1 1 read 8-bit display data (d7 to d0) 0 0 1 8-bit interface 1 1 *1) read 8-bit parameter or status (d7 to d0) 1 0 write 16-bit display data (d15 to d0) or 8-bit parameter (d7 to d0) 0 0 write 8-bit command (d7 to d0) 1 1 read 16-bit display data (d15 to d0) 0 1 1 16-bit interface 1 1 *1) read 8-bit parameter or status (d7 to d0) 1 0 write 9-bit display(d8 to d0) data or 8-bit parameter (d7 to d0) 0 0 write 8-bit command (d7 to d0) 1 1 read 9-bit display data (d8 to d0) 1 0 0 9-bit interface 1 1 *1) read 8-bit parameter or status (d7 to d0) 1 0 write 18-bit display data (d17 to d0) or 8-bit parameter (d7 to d0) 0 0 write 8-bit command (d7 to d0) 1 1 read 18-bit display data (d17 to d0) 1 1 0 18-bit interface 1 1 *1) read 8-bit parameter or status (d7 to d0) note: ? ? = falling edge *1) applied for command code: dah, dbh, dch, 0ah, 0bh, 0ch, 0dh, 0eh, 0fh, 04h and 09h www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 16 confidential leadis technology the parallel interface timing diagram is given in fig. 5.1.5 and fig. 5.1.6. cmd pa 1 cmd pa n-2 pa n-1 cmd csb dc rw e d[k:0] host d[k:0] (mpu to lcd) driver d[k:0] (lcd to mpu) 1-byte command 2-byte command n-byte command (number of parameter = n-1) s p cmd pa 1 cmd pa n-2 pa n-1 cmd signals on d[k:0], dc, rw and e pins during csb=?h? are ignored. cmd pa 1 cmd pa n-2 pa n-1 cmd hi-z pa 1 pa 1 pa 1 cmd: write command code pa: write parameter or ram data [k:0] : k means the used data bus. refer to table 5.1.4 fig. 5.1.5 6800-series parallel bus protocol, write to register or display ddram www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 17 confidential leadis technology dm pa cmd data cmd read parameter read display ram data s p csb dc rw e d[k:0] host d[k:0] (mpu to lcd) driver d[k:0] (lcd to mpu) dm data signals on d[k:0], dc, rdb and wrb pins during csb=?h? are ignored. dm cmd cmd pa dm pa pa hi-z cmd cmd hi-z dm pa dm pa pa hi-z hi-z hi-z hi-z cmd: write command code pa: write parameter or ram data [k:0] : k means the used data bus. refer to table 5.1.3 fig. 5.1.6 6800-series parallel bus protocol, read from register www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 18 confidential leadis technology 5.1.5 serial interface communication with the microprocessor can also be done via a clock-synchronized serial peripheral interface. the selection of this interface is done when all of bs2, bs1 and bs0 are ?l? state (vss1). the serial interface is a 3-pin or 4-pin bi-directional interface for communication between the micro controller and the lcd driver chip. the 3-pin serial use: sceb (chip enable), scl (serial clock) and sda (serial data input/output) and 4-pin serial use: sceb (chip enable), dc (data / command select), scl (serial clock) and sda (serial data input/output). serial clock (scl) is controlled for interface only by mpu, so it can be stopped when the communication is not necessary. 5.1.5.1 write mode the write mode of the interface means the micro controller writes commands and data to the LDS285. 3-pin serial data packet contains a control bit dc and a transmission byte and in 4-pin serial case, data packet contains just transmission byte and control bit dc is transferred by the dc pin. if dc is ?l?, the transmission byte is interpreted as a command byte. if dc is ?h?, the transmission byte is stored in the display data ram (memory write command), or command register as a parameter. any instruction can be sent in any order to the LDS285. the msb is transmitted first. the serial interface circuits are initialized when the sceb is ?h? state. in this initialize state, scl clock pulse or sda data inputs have no effect. a falling edge of sceb enables the serial interface and indicates the start of data transmission. 3-line serial data stream format dc d7 d6 d5 d4 d3 d2 d1 d0 dc dc dc 4-line serial data stream format d7 d6 d5 d4 d3 d2 d1 d0 tb tb tb transmission byte (tb) may be a command or a data msb lsb transmission byte (tb) may be a command or a data msb lsb tb tb tb fig. 5.1.7 serial data stream, write mode when sceb is ?h? state, scl clock is ignored. during the high time of sceb the serial interface is initialized. at the falling sceb edge, scl can be high or low (see fig 5.1.8 ). sda is sampled at the rising edge of scl. dc indicates, whether the byte is command code (dc=0) or parameter/ddram data (dc=1). it is sampled when first rising scl edge (3-line serial interface) or 8 th rising sclk edge (4-line serial interface). if sceb stays low after the last bit of command/data byte, the serial interface expects the dc bit (3-line serial interface) or d7 (4-line serial interface) of the next byte at the next rising edge of scl. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 19 confidential leadis technology 1) 3-pin serial interface protocol 2) 4-pin serial interface protocol tb sceb scl sda 0 d7 d6 d5 d4 d3 d2 d1 d0 d/!c d7 d6 d5 d4 d3 d2 d1 d0 tb s p command command / parameter host (mpu to driver) sceb can be ?h? between parameter / command and parameter / command, but scl and sda during sceb = ?h? is invalid sceb scl sda dc host (mpu to driver) tb d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 tb s p command command / parameter sceb can be ?h? between parameter / command and parameter / command, but scl and sda during sceb = ?h? is invalid d/!c fig. 5.1.8 serial bus protocol, write to register with control bit in transmission www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 20 confidential leadis technology 5.1.5.2 read mode the read mode of the interface means that the micro controller reads register value from the LDS285. to do so the micro controller first has to send a command (read id or read register command) and then the following byte is transmitted in the opposite direction. after that, sceb is required to go high before a new command is send (see fig. 5.1.9 and fig. 5.1.10 ). the LDS285 samples the sda (input data) at the rising edges, but shifts sda (output data) at the falling scl edges. thus the micro controller is supported to read data at the rising scl edges. after the read status command has been sent, the sda line must be set to tri-state no later than at the falling scl edge of the last bit (see fig. 5.1.9 and fig. 5.1.10 ). 3-pin serial protocol (for rdid1/rdid2/rdid3/0ah/0bh/0ch/0dh/0eh/0fh command: 8-bit read) 3-pin serial protocol (for rddid command: 24-bit read) 3-pin serial protocol (for rddst command: 32-bit read) tb sceb scl sda (sdi) sda (sdo) dc d7 d6 d5 d4 d3 d2 d1 d0 tb d20 d19 d3 d2 d1 d0 p s s dc d23 d22 d21 dummy clock cycle tb sceb scl sda (sdi) sda (sdo) dc d7 d6 d5 d4 d3 d2 d1 d0 tb d28 d27 d3 d2 d1 d0 p s s dc d31 d30 d29 dummy clock cycle tb sceb scl sda (sdi) sda (sdo) dc d7 d6 d5 d4 d3 d2 d1 d0 tb d7 d6 d5 d4 d3 d2 d1 d0 p s s dc high-z high-z high-z high-z high-z high-z host driver host driver host driver fig. 5.1.9 serial bus protocol, read mode (3-pin serial interface case) www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 21 confidential leadis technology 4-pin serial protocol (for rdid1/rdid2/rdid3/0ah/0bh/0ch/0dh/0eh/0fh command: 8-bit read) 4-pin serial protocol (for rddid command: 24-bit read) 4-pin serial protocol (for rddst command: 32-bit read) tb d7 d6 d5 d4 d3 d2 d1 d0 tb d7 d6 d5 d4 d3 d2 d1 d0 p s s high-z high-z sceb scl dc sda (sdi) sda (s d o) host driver d7 0 tb d7 d6 d5 d4 d3 d2 d1 d0 tb d20 d19 d3 d2 d1 d0 p s s d23 d22 d21 dummy clock cycle high-z high-z d7 sceb scl dc sda (sdi) sda ( sdo ) host driver 0 tb d7 d6 d5 d4 d3 d2 d1 d0 tb d28 d27 d3 d2 d1 d0 p s s d31 d30 d29 dummy clock cycle high-z high-z d7 sceb scl dc sda (sdi) sda (s d o) host driver 0 fig. 5.1.10 serial bus protocol, read mode (4-pin serial interface case) www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 22 confidential leadis technology 5.1.6 interface pause it will be possible when transferring a command, ddram data or multiple parameter data to invoke a pause in the data transmission. if the chip select line (csb) is released after a whole byte of a ddram data or multiple parameter data has been completed, then LDS285 will wait and continue the ddram data or parameter data transmission from the point where it was paused. if the chip select line is released after a whole byte of a command has been completed, then the display module will receive either the command?s parameters (if appropriate) or a new command when the chip select line is next enabled as shown below. this applies to the following 4 conditions: 1) command-pause-command 2) command-pause-parameter 3) parameter-pause-command 4) parameter-pause-parameter 5.1.6.1 parallel interface pause csb dc rdb wrb d[7:0] d7 to d0 command / parameter d7 to d0 pause command / parameter pause fig. 5.1.11 parallel bus protocol, write mode ? paused by csb 5.1.6.2 serial interface pause sceb scl sda tb d6 d5 d4 d3 d2 d1 d0 dc d7 d6 d5 d4 d3 d2 d1 d0 p host (mpu to driver) dc d7 s command / parameter / data tb pause scl and sda during csb = ?h? is invalid command / parameter / data fig. 5.1.12 serial bus protocol, write mode ? paused by sceb (3-pin serial case) www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 23 confidential leadis technology 5.1.7 data transfer recovery if there is a break in data transmission by resb pulse, while transferring a command or ddram data or multiple parameter command data, before bit d0 of the byte has been completed, then LDS285 will reject the previous bits and have reset the interface such that it will be ready to receive command data again when the chip select line (sceb) is next activated after resb have been high state. see the following example (see fig. 5.1.13 ) if there is a break in data transmission by sceb pulse, while transferring a command or ddram data or multiple parameter command data, before bit d0 of the byte has been completed, then LDS285 will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (sceb) is next activated. see the following example (see fig. 5.1.14 ) s sceb resb scl sda tb dc d7 d6 d5 d4 d3 d2 dc d7 d6 d5 d4 d3 d2 d1 d0 p host (mpu to driver) command / parameter / data command scl and sda during resb = ?l? is invalid and next byte becomes c ommand wait for more than 10 fig. 5.1.13 serial bus protocol, write mode ? interrupted by resb sceb scl sda tb d6 d5 d4 dc d7 d6 d5 d4 d3 d2 d1 d0 p host (mpu to driver) dc d7 s command / parameter / data tb break command / parameter / data fig. 5.1.14 serial bus protocol, write mode ? interrupted by sceb www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 24 confidential leadis technology if 1, 2 or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. the interface is ready to receive next byte as shown in fig. 5.1.15 . cmd1 para11 para12 para13 para12 para11 cmd1 break command1 with 1 s t parameter (para11) should be executed again to write remained paramete r (para12 and para13) cmd2 para11 is sucessfully sended but para12 is breaked and need to be transfered again fig. 5.1.15 write interrupt recovery (serial interface) if a 2 or more parameter command is being sent and a break occurs by the other command before the last one is sent, then the parameters that were successfully sent are stored and the other parameter of that command remains previous value. cmd1 para11 para12 para13 para11 cmd1 break command1 with 1 s t parameter (para11) should be executed again to write remained paramete r (para12 and para13) cmd2 para11 is sucessfully sent but the other parameters are not sent and break happeds by the othe r command. fig. 5.1.16 write interrupt recovery (both serial and parallel interface) www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 25 confidential leadis technology 5.1.8 display module data transfer modes the module has two kinds color modes for transferring data to the display ram. these are 18-bit color per pixel and 24-bit color per pixel. the data format is described for each interface. data can be downloaded to the ddram by 2 methods. 5.1.8.1 method 1 the image data is sent to the ddram in successive frame writes, each time the ddram is filled, the ddram pointer is reset to the start point and the next frame is written. 5.1.8.2 method 2 image data is sent and at the end of each ddram download, a command is sent to stop ddram write. then start memory write command is sent, and a new frame is downloaded. note: 1) these apply to all data transfer color modes on both serial and parallel interfaces. 2) the ddram can contain both odd and even number of pixels for both methods. only complete pixel data will be stored in the ddram. start ddram write image data frame 1 image data frame 2 image data frame 3 any command start stop start ddram write image data frame 1 any command start ddram write any command start stop image data frame 2 any command www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 26 confidential leadis technology 5.2 display data ram (ddram) the LDS285 has an integrated 240x320x24-bit graphic type static ram. this 1.84m-bit memory allows to store on-chip a 240xrgbx320 image with an 24-bpp resolution (16m-color). there will be no abnormal visible effect on the display when there is a simultaneous panel read and interface read or write to the same location of the ddram. display data ram organization column address counter display data ram (240 x 320 x 24-bit) latch row address counter line address counter mpu i/f data gen. ( data sum-up and expand) host interface lcd glass (240 x 320 x rgb) scan address counter www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 27 confidential leadis technology 5.2.1 display data formats 5.2.1.1 serial interface mode (3-pin serial i/f) different display data formats are available for two colors depth supported by the LDS285 listed below. 262k colors, rgb 6-6-6-bits input (see table 5.2.1 ) 16m colors, rgb 8-8-8-bits input (see table 5.2.2 ) table 5.2.1 write data for rgb 6-6-6-bits input note: 1 pixel data with the 18-bit color depth information. the most significant bits are: rx5, gx5 and bx5. the least significant bits are: rx0, gx0 and bx0. frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] lsb ex p ansion sd a scl 1 r1 1 r1 0 r1 4 r1 3 r1 5 r1 2 1 g1 1 g1 0 g1 4 g1 3 g1 5 g1 2 1 b1 1 b1 0 b1 4 b1 3 b1 5 b1 2 18-bit 24-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 28 confidential leadis technology table 5.2.2 write data for rgb 8-8-8-bits input note: 1 pixel data with the 24-bit color depth information. the most significant bits are: rx7, gx7 and bx7. the least significant bits are: rx0, gx0 and bx0. frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 sd a scl 1 1 1 24-bit r1 3 r1 2 r1 6 r1 5 r1 7 r1 4 r1 1 r1 0 g1 3 g1 2 g1 6 g1 5 g1 7 g1 4 g1 1 g1 0 b1 3 b1 2 b1 6 b1 5 b1 7 b1 4 b1 1 b1 0 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 29 confidential leadis technology 5.2.1.2 8-bit parallel interface mode different display data formats are available for two colors depth supported by the LDS285 listed below. 262k colors, rgb 6-6-6-bits input (see table 5.2.3 ) 16m colors, rgb 8-8-8-bits input (see table 5.2.4 ) read (see table 5.2.5 ) table 5.2.3 write data for rgb 6-6-6-bits input ?x? : don?t care 262k color data dc d7 d6 d5 d4 d3 d2 d1 d0 memory write memwr 0 memory write command code - 1 st write 1 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 x x - 2 nd write 1 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 x x - 3 rd write 1 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 x x 1 st pixel data (r1/g1/b1) 4 th write 1 r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 x x - 5 th write 1 g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 x x - 6 th write 1 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 x x 2 nd pixel data (r2/g2/b2) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 note: 3 times transfer is used to transmit 1 pixel data with the 18-bit color depth information. the most significant bits are: rx5, gx5 and bx5. the least significant bits are: rx0, gx0 and bx0. db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] lsb ex p ansion 18-bit 18-bit 24-bit 24-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 30 confidential leadis technology table 5.2.4 write data for rgb 8-8-8-bits input ?x? : don?t care 262k color data dc d7 d6 d5 d4 d3 d2 d1 d0 memory write memwr 0 memory write command code - 1 st write 1 r1 7 r1 6 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 - 2 nd write 1 g1 7 g1 6 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 - 3 rd write 1 b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 1 st pixel data (r1/g1/b1) 4 th write 1 r2 7 r2 6 r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 - 5 th write 1 g2 7 g2 6 g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 - 6 th write 1 b2 7 b2 6 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 2 nd pixel data (r2/g2/b2) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 note: 3 times transfer is used to transmit 1 pixel data with the 18-bit color depth information. the most significant bits are: rx5, gx5 and bx5. the least significant bits are: rx0, gx0 and bx0. 24-bit 24-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 31 confidential leadis technology table 5.2.5 read ?x? : don?t care note: 3 times transfer is used to transmit 1 pixel data with the 24-bit color depth information. the read data can be different to the written data because of the lsb expansion. 16m color data dc d7 d6 d5 d4 d3 d2 d1 d0 memory read memrd 0 memory read command code - dummy 1 x x x x x x x x 1 st read 1 r1 7 r1 6 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 - 2 nd read 1 g1 7 g1 6 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 - 3 rd read 1 b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 1 st pixel data (r1/g1/b1) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 24-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 32 confidential leadis technology 5.2.1.3 9-bit parallel interface mode different display data formats are available for two colors depth supported by the LDS285 listed below. 262k colors, rgb 6-6-6-bits input (see table 5.2.6 ) 16m colors, rgb 8-8-8-bits input (see table 5.2.7 ) read (see table 5.2.8 ) table 5.2.6 write data for rgb 6-6-6-bits input ?x? : don?t care 262k color data dc d8 d7 d6 d5 d4 d3 d2 d1 d0 memory write memwr 0 x memory write command code - 1 st write 1 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 g1 5 g1 4 g1 3 - 2 nd write 1 g1 2 g1 1 g1 0 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 -1 st pixel data (r1/g1/b1) 3 rd write 1 r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 g2 5 g2 4 g2 3 4 th write 1 g2 2 g2 1 g2 0 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 -2 nd pixel data (r2/g2/b2) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 note: 3 times transfer is used to transmit 1 pixel data with the 18-bit color depth information. the most significant bits are: rx5, gx5 and bx5. the least significant bits are: rx0, gx0 and bx0. db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] lsb ex p ansion 24-bit 24-bit 18-bit 18-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 33 confidential leadis technology table 5.2.7 write data for rgb 8-8-8-bits input ?x? : don?t care 262k color data dc d8 d7 d6 d5 d4 d3 d2 d1 d0 memory write memwr 0 memory write command code - 1 st write 1 x r1 7 r1 6 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 - 2 nd write 1 x g1 7 g1 6 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 - 3 rd write 1 x b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 1 st pixel data (r1/g1/b1) 4 th write 1 x r2 7 r2 6 r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 - 5 th write 1 x g2 7 g2 6 g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 - 6 th write 1 x b2 7 b2 6 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 2 nd pixel data (r2/g2/b2) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 note: 3 times transfer is used to transmit 1 pixel data with the 18-bit color depth information. the most significant bits are: rx5, gx5 and bx5. the least significant bits are: rx0, gx0 and bx0. 24-bit 24-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 34 confidential leadis technology table 5.2.8 read ?x? : don?t care note: 3 times transfer is used to transmit 1 pixel data with the 24-bit color depth information. the read data can be different to the written data because of the lsb expansion. frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 16m color data dc d8 d7 d6 d5 d4 d3 d2 d1 d0 memory read memrd 0 x memory read command code - dummy 1 x x x x x x x x x 1 st read 1 r1 7 r1 6 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 x - 2 nd read 1 g1 7 g1 6 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 x - 3 rd read 1 b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 x 1 st pixel data (r1/g1/b1) 24-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 35 confidential leadis technology 5.2.1.4 16-bit parallel interface mode different display data formats are available for two colors depth supported by the LDS285 listed below. 262k colors, rgb 6-6-6-bits input (see table 5.2.9 ) 16m colors, rgb 8-8-8-bits input (see table 5.2.10 ) read (see table 5.2.11 ) table 5.2.9 write data for rgb 6-6-6-bits input in 16-bit parallel interface ?x? : don?t care 262k color data dc d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 memory write memwr 0 x memory write command code - 1 st write 1 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 xx g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 x x - 2 nd write 1 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 xx r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 x x 1 st pixel (r1/g1/b1) 3 rd write 1 g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 xx b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 x x 2 nd pixel (r2/g2/b2) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 note: 3 times transfer is used to transmit 2 pixels data or 2 times transfer are used to transmit 1 pixel data with the 18-bit color depth information.. the most significant bits are: rx5, gx5 and bx5. the least significant bits are: rx0, gx0 and bx0. db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] lsb ex p ansion 18-bit 18-bit 24-bit 24-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 36 confidential leadis technology table 5.2.10 write data for rgb 8-8-8-bits input in 16-bit parallel interface ?x? : don?t care 16m color data dc d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 memory write memwr 0 x memory write command code - 1 st write 1 r1 7 r1 6 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 g1 7 g1 6 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 - 2 nd write 1 b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 r2 7 r2 6 r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 1 st pixel (r1/g1/b1) 3 rd write 1 g2 7 g2 6 g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 b2 7 b2 6 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 2 nd pixel (r2/g2/b2) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 note: 3 times transfer is used to transmit 2 pixels data or 2 times transfer are used to transmit 1 pixel data with the 24-bit color depth information.. the most significant bits are: rx7, gx7 and bx7. the least significant bits are: rx0, gx0 and bx0. 24 bit 24 bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 37 confidential leadis technology table 5.2.11 read ?x? : don?t care note: 3 times transfer is used to transmit 2 pixels data or 2 times transfer are used to transmit 1 pixel data with the 24-bit color depth information.. the read data can be different to the written data because of the lsb expansion. frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 16m color data dc d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 memory read memrd 0 x memory read command code - dummy 1 x x xx x x xxxxxxxxx x 1 st read 1 r1 7 r1 6 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 g1 7 g1 6 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 - 2 nd read 1 b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 r2 7 r2 6 r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 1 st pixel (r1/g1/b1) 3 rd read 1 g2 7 g2 6 g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 b2 7 b2 6 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 2 nd pixel (r2/g2/b2) 24 bit 24 bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 38 confidential leadis technology 5.2.1.5 18-bit parallel interface mode different display data formats are available for four colors depth supported by the LDS285 listed below. 262k colors, rgb 6-6-6-bits input (see table 5.2.12 ) 16m colors, rgb 6-6-6-bits input (see table 5.2.13 ) read (see table 5.2.14 ) table 5.2.12 write data for rgb 6-6-6-bits input in 18-bit parallel interface ?x? : don?t care 2 62k colo r data dc d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 memory write memwr 0 x memory write command code - 1 st write 1 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 -1 st pixel (r1/g1/b1) 2 nd write 1 r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 2 nd pixel (r2/g2/b2) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 note: 3 times transfer is used to transmit 2 pixels data or 2 times transfer are used to transmit 1 pixel data with the 18-bit color depth information.. the most significant bits are: rx5, gx5 and bx5. the least significant bits are: rx0, gx0 and bx0. db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] lsb ex p ansion 18-bit 18-bit 24-bit 24-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 39 confidential leadis technology table 5.2.13 write data for rgb 8-8-8-bits input in 18-bit parallel interface ?x? : don?t care 16m colo r data dc d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 memory write memwr 0 x memory write command code - 1 st write 1 x x r1 7 r1 6 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 g1 7 g1 6 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 - 2 nd write 1 x x b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 r2 7 r2 6 r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 1 st pixel (r1/g1/b1) 3 rd write 1 x x g2 7 g2 6 g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 b2 7 b2 6 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 2 nd pixel (r2/g2/b2) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 note: 3 times transfer is used to transmit 2 pixels data or 2 times transfer are used to transmit 1 pixel data with the 24-bit color depth information.. the most significant bits are: rx7, gx7 and bx7. the least significant bits are: rx0, gx0 and bx0. 24 bit 24 bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 40 confidential leadis technology table 5.2.14 read ?x? : don?t care note: 3 times transfer is used to transmit 2 pixels data or 2 times transfer are used to transmit 1 pixel data with the 24-bit color depth information.. the read data can be different to the written data because of the lsb expansion. frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 16m colo r data dc d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 memory read memrd 0 x memory read command code - dummy 1 x x x x x x x xxxxxxxxxx x 1 st read 1 r1 7 r1 6 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 x g1 7 g1 6 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 x - 2 nd read 1 b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 x r2 7 r2 6 r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 x 1 st pixel (r1/g1/b1) 3 rd read 1 g2 7 g2 6 g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 x b2 7 b2 6 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 x 2 nd pixel (r2/g2/b2) 24 bit 24 bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 41 confidential leadis technology 5.2.2 rgb interface for direct interface with both graphic controller and mpu, LDS285 offers rgb interface mode to receive video data. in rgb interface mode, video data bus becomes (d23 to d1, vd0) and grahic controller can write 24-bit rgb data to predefined row and column address area (by caset and raset command) of the ddram. command and parameter to control LDS285 can be accessed by mpu via serial interface mode. 5.2.2.1 rgb interface bus width set all 2-kinds of bus width can be available during rgb interface mode. (selected by the 2 nd parameter of ifmode command: dw). dw d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 bus width 0 r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b7 b6 b5 b4 b3 b2 b1 b0 24-bit data x x x x x x x x x x x x x x x x r7 r6 r5 r4 r3 r2 r1 r0 x x x x x x x x x x x x x x x x g7 g6 g5 g4 g3 g2 g1 g0 1 x x x x x x x x x x x x x x x x b7 b6 b5 b4 b3 b2 b1 b0 8-bit data note: unused rgb data bus must be connected to vss1. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 42 confidential leadis technology - 24-bit rgb interface mode different display data formats are available for four colors depth supported by the LDS285 listed below. 262k colors, rgb 6-6-6-bits input when (see table 5.2.15 ) 16m colors, rgb 8-8-8-bits input when (see table 5.2.16 ) table 5.2.15 write data for rgb 6-6-6-bits input in 24-bit rgb interface 65k color data d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 memory write 1 st write x x r1 5 r1 4 r1 3 r1 2 r1 1 r1 1 0 xx g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 xx b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 1 st pixel (r1/g1/b1) 2 nd write x x r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 xx g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 xx b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 2 nd pixel (r2/g2/b2) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] lsb ex p ansion 18-bit 18-bit 24-bit 24-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 43 confidential leadis technology table 5.2.16 write data for rgb 8-8-8-bits input in 24-bit rgb interface 65k color data d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 memory write 1 st write r1 7 r1 6 r1 5 r1 4 r1 3 r1 2 r1 1 r1 1 0 g1 7 g1 6 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 1 st pixel (r1/g1/b1) 2 nd write r2 7 r2 6 r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 g2 7 g2 6 g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 b2 7 b2 6 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 2 nd pixel (r2/g2/b2) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 24-bit 24-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 44 confidential leadis technology - 8-bit rgb interface mode different display data formats are available for four colors depth supported by the LDS285 listed below. 262k colors, rgb 6-6-6-bits input when (see table 5.2.17 ) 16m colors, rgb 8-8-8-bits input when (see table 5.2.18 ) table 5.2.17 write data for rgb 6-6-6-bits input in 24-bit rgb interface 65k color data d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 memory write 1 st write x x x x x x x x x x x x x x x x x x r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 2 nd write x x x x x x x x xxxxxxxxxx g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 3 rd write x x x x x x x x x x x x x x x x x x g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 1 st pixel (r1/g1/b1) 4 th write x x x x x x x x x x x x x x x x x x r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 5 th write x x x x x x x x x x x x x x x xxx g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 6 th write x x x x x x x x x x x x x x x x x x b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 2 nd pixel (r1/g1/b1 ) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] db [ 3 ] db [ 2 ] db [ 1 ] db [ 0 ] db [ 5 ] db [ 4 ] lsb ex p ansion 18-bit 18-bit 24-bit 24-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 45 confidential leadis technology table 5.2.18 write data for rgb 8-8-8-bits input in 24-bit rgb interface 65k color data d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 memory write 1 st write x x x x x x x x x x x x x x x x r1 7 r1 6 r1 5 r1 4 r1 3 r1 2 r1 1 r1 0 2 nd write x x x x x x x x xxxxxxxx g1 7 g1 6 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 3 rd write x x x x x x x x x x x x x x x x g1 7 g1 6 g1 5 g1 4 g1 3 g1 2 g1 1 g1 0 1 st pixel (r1/g1/b1) 4 th write x x x x x x x x x x x x x x x x r2 7 r2 6 r2 5 r2 4 r2 3 r2 2 r2 1 r2 0 5 th write x x x x x x x x x x x x xxxx g2 7 g2 6 g2 5 g2 4 g2 3 g2 2 g2 1 g2 0 6 th write x x x x x x x x x x x x x x x x b2 7 b2 6 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 2 nd pixel (r1/g1/b1 ) frame memory r1 g1 b1 r2 g2 b2 r3 g3 b3 24-bit 24-bit www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 46 confidential leadis technology 5.2.2.2 rgb interface mode set all 3-kinds of rgb interface mode can be available to fit the various controller type.(selected by 1 st parameter of ifmode command : if1,if0) rgb i/f mode dck enable video data bus d23 to d1, vd0 vsync vsynco hsync reference clock for display rgb mode1 used used used not used used not used internal oscillator rgb mode2 used used used used not used not used internal oscillator rgb mode3 used used used used not used used dck note: unused rgb data bus must be connected to vss1. rgb interface mode1 data write to the ddram is done by dck and video da ta bus (d23 to d1, vd0) when enable is ?h? state. to make the internal displaying clock, internal oscillator is used. so, to write the video data without flickering, controller needs to tr ansfer the data with synchronous to the vsynco output signal. rgb interface mode2 data write to the ddram is done by dck and video da ta bus (d23 to d1, vd0) when enable is ?h? state. to make the internal displaying clock, internal oscillator is used. but frame display starts with synchronous to vsync input. so, to write the video data without flickers, the graphic controller must always transfer vsync signal to LDS285. rgb interface mode3 data write to the ddram is done by dck and video da ta bus (d23 to d1, vd0) when enable is ?h? state. to make the internal displaying clock, external clocks (dck, vsync and hsync) are used. so, the graphic controller must always transfer dck, vsync and hsync signal to LDS285. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 47 confidential leadis technology te hsync (int) dck enable d17-d1,vd0 serial interface video data write area video data write area still data write area data don?t care data don?t care don?t care data don?t care ram write c ommand a ddress set command mpu data transfer mode a ddress set command rgb transfer 1 mode a ddress set command rgb transfer 1 mode fig. 5.2.1 an example to overwrite still picture data during moving picture display (rgb interface mode1) line no. vsynci bp bp bp 1 2 3 ? 319 320 fp fp fp ? bp bp bp 1 2 3 1 frame wait 1 frame of an external signal start synchronization at the falling edge of the vsynci signal bp bp internal clock line no. vsynci fig. 5.2.2 an example of rgb interface mode2 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 48 confidential leadis technology vsync hsync enable hsync dck enable vd17-vd0 latched data ram wen rgb 0 back p orch front p orch invalid rgb 1 rgb 2 invalid rgb n rgb 0 rgb 1 rgb 2 rgb n fig. 5.2.3 video signal data writing method in rgb interface mode 3 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 49 confidential leadis technology 5.2.3 address counter the address counter sets the addresses of the display data ram for writing and reading. data is written pixel-wise into the ddram matrix of LDS285. the data for one pixel or two pixels is collected (rgb 8-8-8-bit), according to the data formats. as soon as this pixel-data information is complete the ?write access? is activated on the ddram. the locations of ddram are addressed by the address pointers. when mv = 0 ( mv is one of register value controlled by instruction madctl), the address ranges are x=0 to x=239 (0efhex) and y=0 to y=319 (13fh). when mv = 1, the address ranges are x=0 to x=319(13fh) and y=0 to y=239 (0efh). addresses outside these ranges are not allowed. before writing to the ddram, a window where data will be written must be defined. the window is programmable via the command registers xs, ys designating the start address and xe, ye designating the end address. for example the whole display contents will be written, the window is defined by the following values: xs=0 (0h) ys=0 (0h) and xe=239 (0efh), ye=319 (13fh). in vertical addressing mode (mv=1), the y-address increments after each byte, after the last y-address (y=ye), y wraps around to ys and x increments to address the next column. in horizontal addressing mode (mv=0), the x-address increments after each byte, after the last x-address (x=xe), x wraps around to xs and y increments to address the next row. after the every last address (x=xe and y=ye) the address pointers wrap around to address (x=xs and y=ys). for flexibility in handling a wide variety of display architectures, the commands ?caset, raset? and ?madctl? (see section ?6 instruction description?), define flags mx and my, which allows mirroring of the x-address and y-address. all combinations of flags are allowed. fig. 5.2.4 shows the available combinations of writing to the display ram. when mx, my and mv will be changed, the data must be rewritten to the display ram. for each image condition, the controls for the column and row counters apply as below: condition column counter row counter when ramwr/ramrd command is accepted return to ?start column (xs)? return to ?start row (ys)? complete pixel read / write action increment by 1 no change the column counter value is larger than ?end column (xe)? return to ?start column (xs)? increment by 1 the column counter value is larger than ?end column (xe)? and the row counter value is larger than ?end row (ye)? return to ?start column (xs)? return to ?start row (ys)? ( where my= 0 ) www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 50 confidential leadis technology fig. 5.2.4 frame data write direction according to the madctr parameters (mv, mx and my) madctr parameter display data direction mv mx my image in the host (mpu) image in the driver (ddram) normal 0 0 0 y-mirror 0 0 1 x-mirror 0 1 0 x-mirror y-mirror 0 1 1 x-y exchange 1 0 0 x-y exchange y-mirror 1 0 1 x-y exchange x-mirror 1 1 0 x-y exchange x-mirror y-mirror 1 1 1 note: mv=d5 parameter of madctl command, mx=d6 parameter of madctl command, my=d7 parameter of madctl command b e b e b e b e b e b e b e b e b e h/w p osition ( 0 , 0 ) x-y address (0,0) x: caset, y: raset b e h/w p osition ( 0 , 0 ) x-y address (0,0) x: caset, y: raset b e h/w p osition ( 0 , 0 ) x-y address (0,0) x: caset, y: raset b e h/w p osition ( 0 , 0 ) x-y address (0,0) x: caset, y: raset b e h/w p osition ( 0 , 0 ) x-y address (0,0) x: raset, y: caset b e h/w p osition ( 0 , 0 ) x-y address (0,0) x: raset, y: caset b e h/w p osition ( 0 , 0 ) x-y address (0,0) x: raset, y: caset b e h/w p osition ( 0 , 0 ) x-y address (0,0) x: raset, y: caset www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 51 confidential leadis technology 5.2.4 memory map pixel1 pixel2 - - - pixel239 pixel240 source out s1 s2 s3 s4 s5 s6 - - - s715 s716 s717 s718 s719 s720 ra sa my=0 my=1 rgb order ml=0 ml=1 0 319 r0 5-0 g0 5-0 b0 5-0 r1 5-0 g1 5-0 b1 5-0 - - - r238 5-0 g238 5-0 b238 5-0 r239 5-0 g239 5-0 b239 5-0 0 319 1 318 - - - 1 318 2 317 - - - 2 317 3 316 - - - 3 316 4 315 - - - 4 315 5 314 - - - 5 314 6 313 - - - 6 313 7 312 - - - 7 312 8 311 - - - 8 311 9 310 - - - 9 310 10 309 - - - 10 309 11 308 - - - 11 308 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : - - - : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 312 7 - - - 312 7 313 6 - - - 313 6 314 5 - - - 314 5 315 4 - - - 315 4 316 3 - - - 316 3 317 2 - - - 317 2 318 1 - - - 318 1 319 0 - - - rn 5-0 gn 5-0 bn 5-0 319 0 mx=0 0 1 - - - 238 239 ca mx=1 239 238 - - - 1 0 note: ra = row address, ca = column address, sa = scan address, mx = mirror x-axis (column address direction parameter), d6 parameter of madctr command my = mirror y-axis (row address direction parameter), d7 parameter of madctr command ml = scan direction parameter, d4 parameter of madctr command rgb= red, green and blue pixel position change, d3 parameter of madctr command rgb=0 rgb=1 rgb=0 rgb=1 rgb=0 rgb=1 rgb=0 rgb=1 display pattern data www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 52 confidential leadis technology 5.2.5 normal display on or partial mode on in this mode, the content of the frame memory within an area where column pointer is 00h to 0efh and page pointer is 00h to 13fh is displayed. to display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). example1) normal display on example2) partial display on: psl [15:0] = 004h, pel [15:0] = 13ch, madctr (ml)=0 00h 01h 02h 03h 04h .. .. .. echedheehefh s1 s2 s3 s4 s5 : : : s237 s238 s239 s240 000h 00 01 02 03 04 0w 0x 0y 0z 1 st g1 00 01 02 03 04 0w 0x 0y 0z 001h 10 11 12 13 14 1w 1x 1y 1z 2 nd g2 10 11 12 13 14 1w 1x 1y 1z 002h 20 21 22 2x 2y 2z 3 rd g3 20 21 22 2x 2y 2z 003h 30 31 32 3x 3y 3z 4 th g4 30 31 32 3x 3y 3z 004h 40 41 42 4y 4z 5 th g5 40 41 42 4y 4z 005h 50 51 5y 5z 6 th g6 50 51 5y 5z : : : : : : 13ah u0 u1 uy uz 315 th g315 u0 u1 uy uz 13bh v0 v1 v2 vx vy vz 316 th g316 v0 v1 v2 vx vy vz 13ch w0 w1 w2 wx wy wz 317 th g317 w0 w1 w2 wx wy wz 13dh x0 x1 x2 xx xy xz 318 th g318 x0 x1 x2 xx xy xz 13eh y0 y1 y2 y3 y4 y w yx yy yz 319 th g319 y0 y1 y2 y3 y4 yw yx yy yz 13fh z0 z1 z2 z3 z4 zw zx zy zz 320 th g320 z0 z1 z2 z3 z4 zw zx zy zz 320 lines 240 x 320 x 24 bit frame memory 240 x 320 lcd panel scan order displaying area = 320 lines 00h 01h 02h 03h 04h .. .. .. echedheehefh s1 s2 s3 s4 s5 : : : s237 s238 s239 s240 000h 00 01 02 03 04 0w 0x 0y 0z 1 st g1 00 01 02 03 04 0w 0x 0y 0z 001h 10 11 12 13 14 1w 1x 1y 1z 2 nd g2 10 11 12 13 14 1w 1x 1y 1z 002h 20 21 22 2x 2y 2z 3 rd g3 20 21 22 2x 2y 2z 003h 30 31 32 3x 3y 3z 4 th g4 30 31 32 3x 3y 3z 004h 40 41 42 4y 4z 5 th g5 40 41 42 4y 4z 005h 50 51 5y 5z 6 th g6 50 51 5y 5z : : : : : : 13ah u0 u1 uy uz 315 th g315 u0 u1 uy uz 13bh v0 v1 v2 vx vy vz 316 th g316 v0 v1 v2 vx vy vz 13ch w0 w1 w2 wx wy wz 317 th g317 w0 w1 w2 wx wy wz 13dh x0 x1 x2 xx xy xz 318 th g318 x0 x1 x2 xx xy xz 13eh y0 y1 y2 y3 y4 y w yx yy yz 319 th g319 y0 y1 y2 y3 y4 yw yx yy yz 13fh z0 z1 z2 z3 z4 zw zx zy zz 320 th g320 z0 z1 z2 z3 z4 zw zx zy zz 320 lines 240 x 320 x 24 bit frame memory 240 x 320 lcd panel scan order non- displaying area = 4 lines displaying area = 313 lines non- displaying area = 3 lines www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 53 confidential leadis technology 5.2.6 tearing effect output line the tearing effect output line supplies a panel synchronization signal to the mpu. this signal can be enabled or disabled by the tearing effect line off & on commands. the mode of the tearing effect signal is defined by the parameter of the tearing effect line on command. the signal can be used by the mpu to synchronize ddram writing when displaying video images. 5.2.6.1 tearing effect line modes mode 1 , the tearing effect output signal consists of v-blanking information only: t vdl t vdh vertical time scale t vdh = the lcd display is not updated from the ddram t vdl = the lcd display is updated from the ddram (except invisible line ? see below) mode 2 , the tearing effect output signal consists of v-blanking and h-blanking information, there are one v-sync and 320 h-sync pulses per field. t hdl v-sync v-sync t hdh in visible line 1 s t line 2 n d line 319 th line 320 th line t hdh = the lcd display is not updated from the frame memory t hd l = the lcd display is updated from the frame memory (except invisible line ? see above) bottom line top line 2 n d line te (mode2) te (mode1) t vdh note: during sleep in mode, the tearing output pin is active low www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 54 confidential leadis technology 5.2.6.2 tearing effect line timing the tearing effect signal is described below: t vdl t vdh t hdl t hdh vertical timing horizontal timing table 5.2.19 ac characteristics of tearing effect signal idle mode off (frame rate = 59hz) symbol parameter min max unit description t vdl vertical timing low duration tbd - ms t vdh vertical timing high duration 1000 - ? t hdl horizontal timing low duration tbd - ? t hdh horizontal timing high duration tbd 500 ? note: the timings in table 5.2.12 apply when madctl ml=0 and ml=1 the signal?s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. tf tr 0.8*vdd1 0.2*vdd1 0.8*vdd1 0.2*vdd1 the tearing effect output line is fed back to the mpu and should be used as shown below to avoid tearing effect: www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 55 confidential leadis technology 5.2.6.3 example 1: mpu write is faster than panel read. im a g e on lcd mcu to memory te output signal memory to lcd a d c b tim e tim e tim e 1 s t 320 th 320 th 1 s t data write to frame memory is now synchronized to the panel scan. it should be written during the vertical sync pulse of the tearing effect output line. this ensures that data is always written ahead of the panel scan and each panel frame refresh has a complete new image: b b b a a b data to be sent image on lcd a b c d www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 56 confidential leadis technology 5.2.6.4 example 2: mpu write is slower than panel read. im a g e on lcd mcu to memory te output signal memory to lcd a d c b tim e tim e tim e 1 s t 320 th 320 th 1 s t e f the mpu to frame memory write begins just after panel read has commenced i.e. after one horizontal sync pulse of the tearing effect output line. this allows time for the mpu to download the image behind the panel read pointer and to finish downloading during the subsequent frame before the read pointer ?catches? the mpu to frame memory write position. data to be sent image on lcd b a a b a a a b a b c d e f www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 57 confidential leadis technology 5.3 instruction decoder & register the instruction decoder identifies command words arriving at the interface and routes the following data type bytes to their destination. the command set can be found in ?6 instruction description? section. 5.4 system clock generator the timing generator produces the various signals to drive the internal circuitry. internal chip operation is not affected by operations on the data bus. 5.5 oscillator LDS285 has on-chip oscillator which does not require external components. this oscillator output signal is used for system clock generation for internal display operation 5.6 source driver the source driver block includes 240x3 source outputs (s1 to s720), which should be connected directly to the tft-lcd. the source output signals are generated in the data processing block after the data is read out of the ram and latched, which represent the simultaneous selected rows. when less then 720 sources are required the unused source outputs should be left open-circuit. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 58 confidential leadis technology 5.7 gate driver the gate driver block includes 320 gate outputs (g1 to g320) which should be connected directly to the tft-lcd. s1~720 g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 vgl vgh 11 12 10 9 8 7 6 5 4 3 2 1 13 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 59 confidential leadis technology 5.8 rgb interface timing diagram 5.8.1 relationship between input signal and output signal (rgb i/f mode 3) 9 10 1 h ( period is selectable by setting register value ) mck no (internal). s1~s720 hsync 1 2 3 4 5 6 7 8 20 21 22 23 24 25 26 mck (internal) dck hsync 1 2 3 4 5 6 7 8 gn gn+1 gate output disable time gate output on time gate output off time 17 18 19 1 2 3 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 60 confidential leadis technology 5.8.2 input / output timing chart (g0->g320, s1->s720) horizontal valid data start time=10dck, vertical valid data start time=3hsync, 1 line scan, line inversion. hsync vsync data 0 (dummy) data hsync dck enable g0 322 g1 g319 g320 1 2 3 238 239 240 g0 g1 1?st line data 2?nd line data s1~s720 gate output disable time hsync back porch (can be selected by enable pad input) data for s1 to s3 data for s4 to s6 1 2 3 4 5 6 7 8 9 10 11 12 260 259 258 257 256 255 254 253 252 251 250 vsync back porch (can be selected by register setting: vbp[5:0]) 249 152 1 2 1 2 invalid data 239 240 invalid data data for s718 to s720 vcom hsync dck data 323 324 325 326 1 2 3 4 5 6 7 8 322 323 324 325 326 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 315 316 317 318 319 320 259 260 1 2 3 4 5 6 7 8 9 10 11 249 250 251 252 253 254 255 256 257 258 259 260 1 2 3 4 5 6 7 8 9 10 11 12 249 250 251 252 253 254 255 256 257 258 259 260 1 2 3 4 5 6 7 8 9 10 11 12 (dummy) 1 2 3 238 239 240 1 2 3 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 61 confidential leadis technology 5.9 lcd power generation circuit 5.9.1 lcd power generation scheme 1. the boost voltage generated in LDS285 is shown as below. (case=vs<4.2v) vdd2=2.8v vss2=0v avdd=5.6v(x2vdd2) vr=4.0v vs=4.0v vgh=16v(x4vr) vcl=-2.8v(x-1vdd2) vgl=-12v(x-3vr) vcomh=2.5 ~ 5.5v vcoml=-2.0 ~ 1.0v fig. 5.9.1 lcd power generation scheme1 2. the boost voltage generated in LDS285 is shown as below. (case=vs>4.2v) vdd2=2.8v vss2=0v avdd=6.0v(x3vreg_dc) vr=4.0v vs=4.0v vgh=16v(x4vr) vcl=-2.8v(x-1vdd2) vgl=-12v(x-3vr) vcomh=2.5 ~ 5.5v vcoml=-2.0 ~ 1.0v vreg_dc=2v fig. 5.9.2 lcd power generation scheme2(wide viewing angle) www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 62 confidential leadis technology 5.9.2 various boosting steps the boost steps of each boosting voltage are selected according to how the external capacitors are connected. different booster applications are shown as below. c1p c1m c2p c2m a vdd avdd = 2vdd2 ( dual mode ) avdd = 2vdd2 ( sin g le mode ) c1p c1m c2p c2m a vdd c6p c6m vcl vcl = -1vdd2 vgh = 4vr vgl = -3vr c3p c3m c4p c4m c5p c5m vgl vgh vgh = 3vr vgl = -2vr c4p c4m c5p c5m vgl vgh c3p c3m vgh = 4vr vgl = -2vr c3p c3m c4p c4m c5p c5m vgl vgh vgh = 3vr vgl = -3vr c3p c3m c4p c4m c5p c5m vgl vgh c1p c1m c2p c2m avdd = 3vreg_dc (x3 mode) vreg_dc vdc1 avdd fig. 5.9.3 various boosting step www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 63 confidential leadis technology 5.9.3 gray voltage generator LDS285 supports 4 gamma curves. they can be selected by gamset command(26h). 5.9.3.1 gamma correction curve circuit fig. 5.9.4 gamma correction curve cirsuit r999 r998 r997 r996 vr0 r1 r2 r3 r4 vr1000 gm0 gm4 gm3 2 gm8 0 gm17 5 gm22 3 gm25 1 gm25 5 com g4<1:0> rx0,ry0 dec000 dec_64to1 r dec001 dec_64to1 r dec002 dec_64to1 r dec003 dec_64to1 r dec004 dec_64to1 r dec005 dec_64to1 r dec006 rx1,ry1 dec007 rstring1_dec buf_gamma v 0 v 4 v32 gm 0 gm 4 gm32 v80 gm80 v175 gm175 v223 gm223 v25 1 gm251 v25 5 gm255 v<1:3> dec_8to1<2:0> v<5:31> dec_8to1<26:0> v<224:250> dec_8to1<26:0> v<252:254> dec_8to1<2:0 > rstring 2 g4<1:0> gs0<2:0> gs1<2:0> dec_16to1 gs2<2:0> gs3<2:0> gs4<2:0> gs5<2:0> gs6<2:0> dec_16to1 gs7<2:0> v<33:79> dec_2to1<46:0> g4<1:0> v<81:174> dec_2to1<93:0> v<176:222 > dec_2to1<46:0 > www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 64 confidential leadis technology 5.9.3.2 relationship between ddram data and output voltages. (tbd) output voltage when vs= v vcom = low vcom = high data (hex) gamma 1.0 1.8 2.2 2.5 gamma 1.0 1.8 2.2 2.5 00 v0+ v0- 01 v1+ v1- 02 v2+ v2- 03 v3+ v3- 04 v4+ v4- 05 v5+ v5- 06 v6+ v6- 07 v7+ v7- 08 v8+ v8- 09 v9+ v9- 0a v10+ v10- 0b v11+ v11- 0c v12+ v12- 0d v13+ v13- 0e v14+ v14- 0f v15+ v15- 10 v16+ v16- 11 v17+ v17- 12 v18+ v18- 13 v19+ v19- 14 v20+ v20- 15 v21+ v21- 16 v22+ v22- 17 v23+ v23- 18 v24+ v24- 19 v25+ v25- 1a v26+ v26- 1b v27+ v27- 1c v28+ v28- 1d v29+ v29- 1e v30+ v30- 1f v31+ v31- 20 v32+ v32- 21 v33+ v33- 22 v34+ v34- 23 v35+ v35- 24 v36+ v36- 25 v37+ v37- 26 v38+ v38- 27 v39+ v39- 28 v40+ v40- 29 v41+ v41- 2a v42+ v42- 2b v43+ v43- 2c v44+ v44- 2d v45+ v45- 2e v46+ v46- 2f v47+ v47- 30 v48+ v48- 31 v49+ v49- 32 v50+ v50- 33 v51+ v51- 34 v52+ v52- 35 v53+ v53- 36 v54+ v54- 37 v55+ v55- 38 v56+ v56- 39 v57+ v57- 3a v58+ v58- 3b v59+ v59- 3c v60+ v60- 3d v61+ v61- 3e v62+ v62- 3f v63+ v63- 40 v64+ v64- 41 v65+ v65- 42 v66+ v66- 43 v67+ v67- 44 v68+ v68- 45 v69+ v69- 46 v70+ v70- 47 v71+ v71- www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 65 confidential leadis technology 48 v72+ v72- 49 v73+ v73- 4 a v74+ v74- 4b v75+ v75- 4c v76+ v76- 4d v77+ v77- 4e v78+ v78- 4f v79+ v79- 50 v80+ v80- 51 v81+ v81- 52 v82+ v82- 53 v83+ v83- 54 v84+ v84- 55 v85+ v85- 56 v86+ v86- 57 v87+ v87- 58 v88+ v88- 59 v89+ v89- 5a v90+ v90- 5b v91+ v91- 5c v92+ v92- 5d v93+ v93- 5e v94+ v94- 5f v95+ v95- 60 v96+ v96- 61 v97+ v97- 62 v98+ v98- 63 v100+ v100- 64 v101+ v101- 65 v102+ v102- 66 v103+ v103- 67 v104+ v104- 68 v105+ v105- 69 v106+ v106- 6 a v107+ v107- 6b v108+ v108- 6c v109+ v109- 6d v110+ v110- 6e v111+ v111- 6f v112+ v112- 70 v113+ v113- 71 v114+ v114- 72 v115+ v115- 73 v116+ v116- 74 v117+ v117- 75 v118+ v118- 76 v119+ v119- 77 v120+ v120- 78 v121+ v121- 79 v122+ v122- 7 a v123+ v123- 7b v124+ v124- 7c v125+ v125- 7d v126+ v126- 7e v127+ v127- 7f v127+ v127- 80 v128+ v128- 81 v129+ v129- 82 v130+ v130- 83 v131+ v131- 84 v132+ v132- 85 v133+ v133- 86 v134+ v134- 87 v135+ v135- 88 v136+ v136- 89 v137+ v137- 8 a v138+ v138- 8b v139+ v139- 8c v140+ v140- 8d v141+ v141- 8e v142+ v142- 8f v143+ v143- 90 v144+ v144- 91 v145+ v145- 92 v146+ v146- 93 v147+ v147- 94 v148+ v148- 95 v149+ v149- www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 66 confidential leadis technology 96 v150+ 2.097 v150- 97 v151+ 2.056 v151- 98 v152+ 2.015 v152- 99 v153+ 1.975 v153- 9 a v154+ 1.934 v154- 9b v155+ 1.893 v155- 9c v156+ 1.853 v156- 9d v157+ 1.817 v157- 9e v158+ 1.782 v158- 9f v159+ 1.746 v159- a 0 v160+ 1.711 v160- a 1 v161+ 1.676 v161- a 2 v162+ 1.640 v162- a 3 v163+ 1.605 v163- a 4 v164+ 1.575 v164- a 5 v165+ 1.545 v165- a 6 v166+ 1.515 v166- a 7 v167+ 1.485 v167- a 8 v168+ 1.455 v168- a 9 v169+ 1.425 v169- a a v170+ 1.395 v170- a b v171+ 1.363 v171- a c v172+ 1.330 v172- a d v173+ 1.298 v173- a e v174+ 1.265 v174- a f v175+ 1.233 v175- b0 v176+ 1.200 v176- b1 v177+ 1.166 v177- b2 v178+ 1.131 v178- b3 v179+ 1.097 v179- b4 v180+ 1.062 v180- b5 v181+ 1.028 v181- b6 v182+ 0.985 v182- b7 v183+ 0.943 v183- b8 v184+ 0.900 v184- b9 v185+ 0.851 v185- b a v186+ 0.803 v186- bb v187+ 0.750 v187- bc v188+ 0.683 v188- bd v189+ 0.608 v189- be v190+ 0.518 v190- bf v191+ 0.368 v191- c0 v192+ 3.540 v192- c1 v193+ 3.398 v193- c2 v194+ 3.383 v194- c3 v195+ 3.353 v195- c4 v196+ 3.293 v196- c5 v197+ 3.203 v197- c6 v198+ 3.128 v198- c7 v199+ 3.053 v199- c8 v200+ 2.963 v200- c9 v201+ 2.873 v201- c a v202+ 2.783 v202- cb v203+ 2.717 v203- cc v204+ 2.651 v204- cd v205+ 2.585 v205- ce v206+ 2.519 v206- cf v207+ 2.453 v207- d0 v208+ 2.400 v208- d1 v209+ 2.348 v209- d2 v210+ 2.295 v210- d3 v211+ 2.243 v211- d4 v212+ 2.190 v212- d5 v213+ 2.138 v213- d6 v214+ 2.097 v214- d7 v215+ 2.056 v215- d8 v216+ 2.015 v216- d9 v217+ 1.975 v217- d a v218+ 1.934 v218- db v219+ 1.893 v219- dc v220+ 1.853 v220- dd v221+ 1.817 v221- de v222+ 1.782 v222- df v223+ 1.746 v223- e0 v224+ 1.711 v224- e1 v225+ 1.676 v225- e2 v226+ 1.640 v226- e3 v227+ 1.605 v227- www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 67 confidential leadis technology e4 v228+ v228- e5 v229+ v229- e6 v230+ v230- e7 v231+ v231- e8 v232+ v232- e9 v233+ v233- e a v234+ v234- eb v235+ v235- ec v236+ v236- ed v237+ v237- ee v238+ v238- ef v239+ v239- f0 v240+ v240- f1 v241+ v241- f2 v242+ v242- f3 v243+ v243- f4 v244+ v244- f5 v245+ v245- f6 v246+ v246- f7 v247+ v247- f8 v248+ v248- f9 v249+ v249- f a v250+ v250- fb v251+ v251- fc v252+ v252- fd v253+ v253- fe v254+ v254- ff v255+ v255- www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 68 confidential leadis technology gamma curve 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 12 24 36 48 60 72 84 96 108 120 135 147 159 171 183 195 207 219 231 243 255 gamma1.0 gamma1.8 gamma2.2 gamma2.5 fig. 5.9.5 gamma curve according to the gc0 to gc3 bit (tbd) gc0 gc1 gc2 gc3 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 69 confidential leadis technology fig. 5.9.6 relationship between ddram data and output level source output vcom positive negative fig. 5.9.7 relationship between source output and vcom v0+(v255-) v255+(v0-) vs vss 00h 40h 80h c0h ffh www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 70 confidential leadis technology 5.9.4 temperature compensation the LDS285 has a built-in temperature compensation circuits. by the temperature compensation circuits, user can obtain a higher quality in the various temperature ranges. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 71 confidential leadis technology 5.10 power on/off sequence vdd1 and vdd2 can be applied in any order. vdd2 and vdd1 can be powered down in any order. during power off, if lcd is in the sleep out mode, vdd2 and vdd1 must be powered down minimum 120msec after resb has been released. during power off, if lcd is in the sleep in mode, vdd1 or vdd2 can be powered down minimum 0msec after resb has been released. !sce can be applied at any timing or can be permanently grounded. resb has priority over !sce. there will be no damage to the display module if the power sequences are not met. there will be no abnormal visible effects on the display panel during the power on/off sequences. there will be no abnormal visible effects on the display between ending the power on sequence and receiving sleep out command and between receiving sleep in command and starting the power off sequence. if resb line is not held stable by host during power on sequence as defined in sections 5.10.21, and 5.10.2, then it will be necessary to apply a hardware reset (resb) after host power on sequence is complete to ensure correct operation. otherwise function is not guaranteed. the power on/off sequence is illustrated below: 5.10.1 case 1 ? resb line is held high or unstable by host at power on if resb line is held high or unstable by the host during power on, then a hardware reset must be applied after both vdd2 and vdd1 have been applied ? otherwise correct functionality is not guaranteed. there is no timing restriction upon this hardware reset. tr pw = +/- no limit tf pw = +/- no limit time when the latter signal rises up to 90% of its typical value. e.g. when vdd2 comes later, this time is defined at the cross point of 90% of 2.5v/2.75v, not 90% of 2.3v. tr pw!cs = +/- no limit tf pw!cs = +/- no limit time when the former signal falls down to 90% of its typical value. e.g. when vdd2 falls earlier, this time is defined at the cross point of 90% of 2.5v/2.75v, not 90% of 2.3v. vdd1 vdd2 !cs n ote: unless otherwise specified, timings herein show cross point at 50% of signal/power level. h or l !res tr pw!res = + no limit tf pw!res1 = min.120ms tf pw!res2 = min.0ns tf pw!res1 is applied to !res falling in the sleep out mode. tf pw!res2 is applied to !res falling in the sleep in mode . 30% !res 30% (power down in sleep out mode) (power down in sleep in mode) tr pw!res = + no limit fig. 5.10.1 resb line is held high or unstable by host at power on www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 72 confidential leadis technology 5.10.2 case 2 ? resb line is held low by host at power on if resb line is held low (and stable) by the host during power on, then the resb must be held low for minimum 10 sec after both vdd2 and vdd1 have been applied. tr pw = +/- no limit tf pw = +/- no limit time when the latter signal rises up to 90% of its typical value. e.g. when vdd2 comes later, this time is defined at the cross point of 90% of 2.5v/2.75v, not 90% of 2.3v. tr pw!cs = +/- no limit tf pw!cs = +/- no limit time when the former signal falls down to 90% of its typical value. e.g. when vdd2 falls earlier, this time is defined at the cross point of 90% of 2.5v/2.75v, not 90% of 2.3v. vdd1 vdd2 !cs n ote: unless otherwise specified, timings herein show cross point at 50% of signal/power level. h or l !res tr pw!res = min.10 s tf pw!res1 = min.120ms tf pw!res2 = min.0ns tf pw!res1 is applied to !res falling in the sleep out mode. tf pw!res2 is applied to !res falling in the sleep in mode . !res (power down in sleep out mode) (power down in sleep in mode) tr pw!res = min.10 fig. 5.10.2 resb line is held low by host at power on 5.11 uncontrolled power off the uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. there will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. at an uncontrolled power off the display will go blank and there will not be any visible effects within 1 second on the display (blank display) and remains blank until ?power on sequence? powers it up. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 73 confidential leadis technology 5.12 power flow chart for different power modes ptlon noron noron ptlon sleep out normal display mode on idle mode on sleep out normal display mode on idle mode off sleep out partial mode on idle mode on sleep out partial mode on idle mode off sleep in normal display mode on idle mode off sleep in normal display mode on idle mode on sleep in partial mode on idle mode on sleep in partial mode on idle mode off slpin slpout idmon idmoff idmon idmoff power on sequence hw reset sw reset normal display mode on = noron partial mode on = ptlon idle mode off = idmoff idle mode on = idmon sleep out = slpout sleep in = slpin idmon idmoff idmon idmoff slpin slpout slpin slpout slpin slpout ptlon noron noron ptlon sleep out sleep in note 1: there is not any abnormal visual effect when there is changing from one power mode to another power mode. 2: there is not any limitation, which is not specified by this spec, when there is changing from one power mode to another power mode fig. 5.12.1 power flow char for different power modest www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 74 confidential leadis technology 5.13 input / output pin state 5.13.1 output or bi-directional (i/o) pins output or bi-directional pins after power on after hardware reset after software reset te low low low d23 to d0 (output driver) high-z (inactive) high-z (inactive) high-z (inactive) test1, test4 x x x note: there will be no output from d23-d0 during power on/off sequence, hardware reset and software reset. 5.13.2 input pins input pins during power on process after power on after hardware reset after software reset during power off process resb see section 5.10 input valid input valid input valid see section 5.10 csb input invalid input valid inpu t valid input valid input invalid dc input invalid input valid inpu t valid input valid input invalid wrb input invalid input valid inpu t valid input valid input invalid rdb input invalid input valid inpu t valid input valid input invalid d23 to d0 input invalid input valid input valid input valid input invalid vsync, hsync , dck, enable, vd0 input invalid input valid input valid input valid input invalid srgb, sinv, smx,smy, p68, bs2, bs1,bs0, tgs,extc,frm,psel, osc,test2, test3 input invalid input valid input valid input valid input invalid www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 75 confidential leadis technology 5.14 sleep out ?command and self-diagnostic functions of the display module 5.14.1 register loading detection sleep out-command (see section 6.1.13 ?sleep out (11h)?) is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from eeprom (or similar device) to registers of the display controller is working properly. there are compared factory values of the eeprom and register values of the display controller by the display controller. if those both values (eeprom and register values) are same, there is inverted (=increased by 1) a bit, which is defined in command 6.1.11 ?read display self-diagnostic result (0fh)? (=rddsdr) (the used bit of this command is d7). if those both values are not same, this bit (d7) is not inverted (= increased by 1). the flow chart for this internal function is following: note: there is not compared and loaded register values, which can be changed by user (00h to afh and dah to ddh), by the display module. fig. 5.14.1 regist er loading detection flow chart sleep in (10h) sleep out mode sleep in mode sleep out (11h) loads and compares eeprom and register values are eeprom and register values same? d7 inverted rddsdr?s d7=0 power on sequence hw reset sw reset yes no www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 76 confidential leadis technology 5.14.2 functionality detection sleep out-command (see section 6.1.13 ?sleep out (11h)?) is a trigger for an internal function of the display module, which indicates, if the display module is still running and meets functionality requirements. the internal function (= the display controller) is comparing, if the display module is still meeting functionality requirements (e.g. booster voltage levels, timings, etc.). if functionality requirement is met, there is inverted (= increased by 1) a bit, which defined in command 6.1.11 ?read display self- diagnostic result (0fh)? (= rddsdr) (the used bit of this command is d6). if functionality requirement is not same, this bit (d6) is not inverted (= increased by 1). the flow chart for this internal function is following: note: it is needed 120msec after sleep out -command, when there is changing from sleep in ?mode to sleep out -mode, before it is possible to check if functionality requirements are met and a value of rddsdr?s d6 is valid. otherwise, there is 5msec delay for d6?s value, when sleep out ?command is sent in sleep out -mode. fig. 5.14.2 functionality detection flow chart sleep in (10h) sleep out mode sleep in mode sleep out (11h) checks timings, voltage levels and other functionalities is functionality requirement met ? d6 inverted rddsdr?s d6=0 power on sequence hw reset sw reset yes no www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 77 confidential leadis technology 5.14.3 chip attachment detection (optional) sleep out-command (see section 6.1.13 ?sleep out (11h)?) is a trigger for an internal function of the display module, which indicates, if a chip or chips (e.g. driver, etc.) of the display module is/are attached to the circuit route of a flex foil or display glass ito. there is inverted (= increased by 1) a bit, which is defined in command 6.1.11 ?read display self- diagnostic result (0fh)? (= rddsdr) (the used bit of this command is d5), if the chip or chips is/are attached to the circuit route of the flex or display glass. if this chip is or those chips are not attached to the circuit route of the flex or display glass, this bit (d5) is not inverted (= increased by 1). the following figure is for reference purposes; how this chip attachment can be implemented e.g. there are connected together 2 bumps via route of ito or the flex foil on 4 corners of the driver (chip). the flow chart for this internal function is following: fig. 5.14.3 chip attachment detection flow chart sleep in (10h) sleep out mode sleep in mode sleep out (11h) checks, if chip is attached to route is chip attached to routes? d5 inverted rddsdr?s d5=0 power on sequence hw reset sw reset yes no substrate or flex foil bum p routing between bumps routing between bumps throu g h view of driver to bum p s www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 78 confidential leadis technology 5.14.4 display glass break detection (optional) sleep out-command (see section 6.1.12 ?sleep out (11h)?) is a trigger for an internal function of the display module, which indicates, if the display glass of the display module is broken or not. there is inverted (= increased by 1) a bit, which is defined in command 6.1.11 ?read display self-diagnostic result (0fh)? (= rddsdr) (the used bit of this command is d4), if the display glass is not broken. if this display glass is broken, this bit (d4) is not inverted (= increased by 1). the following figure is a reference, how this glass break detection can be implemented e.g. there is connected together 2 bumps via route of ito. this route of ito is the nearest route of the edge of the display glass. the flow chart for this internal function is following: fig. 5.14.4 display glass break detection flow chart slee p in ( 10h ) slee p out mode slee p in mode slee p out ( 11h ) checks, if display glass is broken is the display glass broken? d4 inverted rddsdr?s d4=0 power on sequence hw reset sw reset no yes substrate of dis p la y g lass bum p throu g h view of driver to bum p s active area of the display glass www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 79 confidential leadis technology 6 adaptive bcaklight control and led driver control 6.1 labc ( light adaptive backlight control) 6.1.1 system block diagam with als (ambient light sensor) and LDS285 fig. 6.1.1 system block diagram with als the general block diagram of the ambient light and brightness control is illustrated in fig 6.1.1. the information of the ambient light is sent to LDS285 and the brightness control in LDS285 deals with them if the user enables it. the user can read ambient light information from LDS285 and control the brightness of leds in tft panel by writing the command to LDS285 manually. (see section 7.1.32 ? write display brightness (51h)?). ambient light sensor ambient light from outside mpu brightness conroller messi or lossi ldi driver leds tft panel LDS285 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 80 confidential leadis technology 6.1.2 labc function flow 6.1.2.1 labc contol from sleep out to sleep in z previous status before the sequence - sleep in mode - bctrl = 0, bl = 0 in ?write ctrl display(53h)? z command sequence command : ?sleep out ( 11h)? - not working brightness control - display backlight off command : ?write display brightness (51h)? parameter : dbv[7:0] : 216 (dbh: 85 % brightness ) - not working brightness control - display backlight off command : ?write ctrl display (53h)? parameter : bctrl = 1 : brightness control block on bl = 1 : backlight control on - display waits for v-sync - display starts brightness control from 0 % to 85 % after v-sync command : ?write display brightness (51h)? parameter : dbv[7:0] : 255 (dbh: 100 % brightness ) - display waits for v-sync - display starts brightness control from 85 % to 100 % after v-sync command : ?write ctrl display (53h)? parameter : bctrl = 0 : brightness control block off bl = 0 : backlight control off - display waits for v-sync - display backlight off command : ?sleep in ( 10h)? following fig 6.1.2 shows the brightness changes in the case of the above example.. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 81 confidential leadis technology fig. 6.1.2 labc ( light adaptive brightness control ) example display brightness 100 % 50% 1. s l eep out 2. write display brightness : 85% 3.write ctrl display 6 . s l eep in 4. write display brightness : 100% 5.write ctrl display 0 % 85 % 100 % 0 % command se q uence 85% 100% 0% www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 82 confidential leadis technology 6.2 cabc ( content adaptive backlight control) a content adaptive brightness control function can be used to reduce the power consumption of the luminance source. content adaptation means that content grey level scale can be increased while simultaneously lowering brightness of the backlight to achieve the same perceived brightness. the adjusted grey level scale and thus the power consumption reduction depend on the content of the image. the function and its different modes can be controlled. see ?7.1.36 write content adaptive brightness control (55h)? for more information. definition modes : off mode : content adaptive brightness control functionality is totally off. ui(user interface) image mode : optimized for ui image. it is kept image quality as much as possible. target power consumption reduction ratio: 10% or less si(still picture mode) : optimized for still picture. some image quality degradation would be acceptable. target power consumption reduction ratio: more than 30 % mi(moving image mode) : optimized for moving image. it is focused on the biggest power reduction with image quality degradation. target power consumption reduction ratio : more than 30 % www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 83 confidential leadis technology 6.2.1 cabc function flow content adaptive brightness control operates like below. display brightness is changed, according to the image contents. the following graph in fig 6.2.1 mentions the case of displaying three different images. - image a : -20 % brightness reduction - image b : -30 % brightness reduction - image c : -10 % brightness reduction fig. 6.2.1 cabc (content adaptive brightness control) example ) 6.3 cabc and labc cabc and labc can be ?on? simultaneously. then the final display brightness is calculated with the following formula. display brightness = brighness based on labc * brightness based on cabc table 6.3.1 display brightness ration when labc and cabc are all ?on? labc brightness ratio cabc brightness ratio display brightness ratio case1 85% 80% 68% case2 60% 70% 42% case3 85% 90% 76.5% display brightness 100 % 50 % image a brightness reduction ratio : -20 % image b brightness reduction ratio : -30 % image c brightness reduction ratio : -10 % 80 % 70 % 90 % 0 % www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 84 confidential leadis technology 6.4 led driver control LDS285 can change the brightness of leds in panel by controlling led drivers if labc or cabc is enabled (refer to section 6.1 labc and 6.2 cabc). LDS285 can support the two interfaces for two types of led drivers, led driver with pwm pulse contorl and led driver with 1-wire digital interface (only for lds8661), through the output led_cnt. 6.4.1 led driver control with pwm pulse LDS285 can calculate the backlight brightness level and send it to led driver which is controlled by pwm pulse through the output led_cnt. fig 6.4.1 is the basic timing diagram which is used in LDS285 to contol led driver. fig. 6.4.1 pwm pulse timing on led_cnt output the period t period of pwm pulse can be changed by the 3 rd parameter per[3:0] of the command ?ledctrl(efh)?. (see the section 7.1.55 ledctrl) the led-on time t on and the led-off time t off are decided by the backlight brightness level which is calculated with labc or/and cabc in LDS285. if labc is off and cabc is off, then led_cnt is the same to display-on signal. fig 6.4.2 shows the change of pwm pulse according to per[3:0]. led_cnt dislay_on t period t on t off when labc=1 or cabc =1 when labc=0 and cabc =0 led_cnt www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 85 confidential leadis technology fig. 6.4.2 pwm pulse timing according to per[3:0] fig 6.4.3 shows the two examples of pwm pulse with labc, cabc and per[3:0] fig. 6.4.3 pwm pulse examples with labc, cabc and per[3:0] per[3:0] led_cnt 0 1 2 3 4 5 6 7 8 else t p eriod 1024us 1280ns 1536ns 1792ns 2048ns 3076ns 4096ns 8192ns 512ns 256ns vdd2 vss2 t p eriod case1 : labc brightness ratio = 80%, cabc = off and per[3:0] = 0 case2 : labc brightness ratio = 90%, cabc brightness ration = 80 % and per[3:0] = 4 1024ns led_cnt 819ns ( 1024 * 0.8 ) 205ns ( 1024 * 0.2 ) 2048ns led_cnt 1474ns ( 2048 * 0.9 * 0.8 ) 574ns ( 2048 * 0.28 ) where high level is vdd2 and low level is vss2 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 86 confidential leadis technology 6.4.2 led driver control with 1-wire digital interface( only for lds8861 ) LDS285 can support only the led driver lds8861 with 1-wire digital interface. here we specify the interface between LDS285 and lds8861 briefly. the led_cnt output in LDS285 should be connected to en/set pin in lds8816. fig. 6.4.4 interconnection between LDS285 and lds8861 LDS285 control lds8861 through the one wire programming. the en/set logic input in lds8861 operates as a chip enable and singla wire addressable interface for control and current setting of all leds. LDS285 can write data to lds8861 by programming the 2 nd parameter of the command ?ledctrl(efh)?. (see the section 7.1.55 ledctrl). the 2 nd parameter of the command ?ledctrl(efh)? consists of addr[2:0] and db[3:0]. the user can change the status of lds8861 by changing the 2 nd parameter of the command ?ledctrl(efh)?. fig.6.4.5 shows the timing specification of en/set in lds8861 and LDS285 drives the led_cnt output meeting the timing specification of en/set in lds8861. if you need more detailed specification, please refer to ?the specification of lds8861 ( 6-channel fractional charge pump led driver in 3x3 tqfn). LDS285 lds8861 (led driver) c1- c1+ c2- c2+ vin 2.5v to 5.5v vin en/set leda1 leda2 ledb1 ledb2 ledc1 ledc2 one wire programming led_cnt www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 87 confidential leadis technology symbol name conditions min typ max units t setup en/set setup from shutdown 10 us t lo en/set program low time 0.2 100 us t hi en/set program high time 0.2 100 us t off en/set low time to shutdown 1.5 ms t datadelay en/set delay to data 500 1000 us t resetdelay en/set delay high to address 2 ms fig. 6.4.5 en/set timing specification in lds8861 shutdown t setup t lo t high t datadela t resetdelay t off en/set shutdown address data wait www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 88 confidential leadis technology 7 instruction description 7.1 instruction code 7.1.1 instruction code table table 7.1.1 instruction code ?-?: don?t care instruction refer dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function nop 7.1.2 0 1 - 0 0 0 0 0 0 0 0 (00h) no operation swreset 7.1.3 0 1 - 0 0 0 0 0 0 0 1 (01h) software reset 0 1 - 0 0 0 0 0 1 0 0 (04h) read display id 1 1 - - - - - - - - - - dummy read 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 - id1 read 1 1 - 1 id26 id25 id24 id23 id22 id21 id20 - id2 read rddid 7.1.4 1 1 - id37 id36 id35 id34 id33 id32 id31 id30 - id3 read 0 1 - 0 0 0 0 1 0 0 1 (09h) read display status 1 1 - - - - - - - - - - dummy read 1 1 - st31 st30 st29 st28 st27 st26 st25 st24 - - 1 1 - st23 st22 st21 st20 st19 st18 st17 st16 - - 1 1 - st15 st14 st13 st12 st11 st10 st9 st8 - - rddst 7.1.5 1 1 - st7 st6 st5 st4 st3 st2 st1 st0 - - 0 1 - 0 0 0 0 1 0 1 0 (0ah) read display power mode 1 1 - - - - - - - - - - dummy read rddpm 7.1.6 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 - - 0 1 - 0 0 0 0 1 0 1 1 (0bh) read display madctr 1 1 - - - - - - - - - - dummy read rddmadctr 7.1.7 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 - - 0 1 - 0 0 0 0 1 1 0 0 (0ch) read display pixel format 1 1 - - - - - - - - - - dummy read rddcolmod 7.1.8 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 - - 0 1 - 0 0 0 0 1 1 0 1 (0dh) read display image mode 1 1 - - - - - - - - - - dummy read rddim 7.1.9 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 - - 0 1 - 0 0 0 0 1 1 1 0 (0eh) read display signal mode 1 1 - - - - - - - - - - dummy read rddsm 7.1.10 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 - - 0 1 - 0 0 0 0 1 1 1 1 (0fh) read display self-diagnostic result 1 1 - - - - - - - - - - dummy read rddsdr 7.1.11 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 - - slpin 7.1.12 0 1 - 0 0 0 1 0 0 0 0 (10h) sleep in & booster off slpout 7.1.13 0 1 - 0 0 0 1 0 0 0 1 (11h) sleep out & booster on ptlon 7.1.14 0 1 - 0 0 0 1 0 0 1 0 (12h) partial mode on noron 7.1.15 0 1 - 0 0 0 1 0 0 1 1 (13h) partial off (normal) invoff 7.1.16 0 1 - 0 0 1 0 0 0 0 0 (20h) display inversion off (normal) invon 7.1.17 0 1 - 0 0 1 0 0 0 0 1 (21h) display inversion on 0 1 - 0 0 1 0 0 1 1 0 (26h) gamma curve select gamset 7.1.18 1 1 - gc7 gc6 gc5 gc4 gc3 gc2 gc1 gc0 - - dispoff 7.1.19 0 1 - 0 0 1 0 1 0 0 0 (28h) display off dispon 7.1.20 0 1 - 0 0 1 0 1 0 0 1 (29h) display on 0 1 - 0 0 1 0 1 0 1 0 (2ah) column address set 1 1 - xs15 xs14 xs13 xs12 xs11 xs10 xs9 xs8 - 1 1 - xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 - x address start: 0 xs efh :mv=0 x address start: 0 xs 13fh :mv=1 1 1 - xe15 xe14 xe13 xe12 xe11 xe10 xe9 xe8 - caset 7.1.21 1 1 - xe7 xe6 xe5 xe4 xe3 xe2 xe1 xe0 - x address end: xs xe efh :mv=0 x address end: xs xe 13fh :mv=1 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 89 confidential leadis technology table 7.1.2 instruction code (continued) ?-?:don?t care instruction refer dc w rb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 - 0 0 1 0 1 0 1 1 (2bh) row address set 1 1 - ys15 ys14 ys13 ys12 ys11 ys10 ys9 ys8 - 1 1 - ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 - y address start: 0 ys 13fh :mv=0 y address start: 0 ys efh :mv=1 1 1 - ye15 ye14 ye13 ye12 ye11 ye10 ye9 ye8 - raset 7.1.22 1 1 - ye7 ye6 ye5 ye4 ye3 ye2 ye1 ye0 - y address end: ys ye 13fh :mv=0 y address end: ys ye efh :mv=1 0 1 - 0 0 1 0 1 1 0 0 (2ch) memory write ramwr 7.1.23 1 1 d17-8 d7 d6 d5 d4 d3 d2 d1 d0 - write data 0 1 - 0 0 1 0 1 1 1 0 (2eh) memory read 1 1 - - - - - - - - - - dummy read ramrd 7.1.24 1 1 d17-8 d7 d6 d5 d4 d3 d2 d1 d0 - read data 0 1 - 0 0 1 1 0 0 0 0 (30h) partial start/end address set 1 1 - psl15 psl14 psl13 psl12 psl11 psl10 psl9 psl8 - 1 1 - psl7 psl6 psl5 psl4 psl3 psl2 psl1 psl0 - partial start address (0,1,2 , ?,319) 1 1 - pel15 pel14 pel13 pel12 pel11 pel10 pel9 pel8 - ptlar 7.1.25 1 1 - pel7 pel6 pel5 pel4 pel3 pel2 pel1 pel0 - partial end address (0,1,2 , ?, 319) teoff 7.1.26 0 1 - 0 0 1 1 0 1 0 0 (34h) tearing effect line off 0 1 - 0 0 1 1 0 1 0 1 (35h) tearing effect mode set & on teon 7.1.27 1 1 - - - - - - - - m - m=?0?: mode1, m=?1?: mode2 0 1 - 0 0 1 1 0 1 1 0 (36h) memory data access control madctr 7.1.28 1 1 - my mx mv ml rgb - - - - - idmoff 7.1.29 0 1 - 0 0 1 1 1 0 0 0 (38h) idle mode off idmon 7.1.30 0 1 - 0 0 1 1 1 0 0 1 (39h) idle mode on 0 1 - 0 0 1 1 1 0 1 0 (3ah) interface pixel format colmod 7.1.31 1 1 - - rp2 rp1 rp0 - p2 p1 p0 - interface format 0 1 - 0 1 0 1 0 0 0 1 (51h) write display brightness wrdisbv 7.1.32 1 1 - dbv7 dbv6 dbv5 dbv4 dbv3 dbv2 dbv1 dbv0 write data 0 1 - 0 1 0 1 0 0 1 0 (52h) read display brightness value 1 1 - - - - - - - - - dummy read rddisbv 7.1.33 1 1 - dbv7 dbv6 dbv5 dbv4 dbv3 dbv2 dbv1 dbv0 read parameter 0 1 - 0 1 0 1 0 0 1 1 (53h) write control display wrctrld 7.1.34 1 1 - - - bctrl - - bl - - - write data 0 1 - 0 1 0 1 0 1 0 0 (54h) read control display 1 1 - - - - - - - - - dummy read rdctrld 7.1.35 1 1 - - - bctrl - - bl - - read parameter 0 1 - 0 1 0 1 0 1 0 1 (55h) wrtie content adaptive brightness wrcabc 7.1.36 1 1 - - - c1 c0 - write data 0 1 - 0 1 0 1 0 1 1 0 (56h) read content adaptive brightness 1 1 - - - - - - - - - dummy read rdcabc 7.1.37 1 1 - - - c1 c0 read parameter 0 1 - 1 1 0 1 1 0 1 0 (dah) read id1 1 1 - - - - - - - - - - dummy read rdid1 7.1.38 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 - read parameter 0 1 - 1 1 0 1 1 0 1 1 (dbh) read id2 1 1 - - - - - - - - - - dummy read rdid2 7.1.39 1 1 - 1 id26 id25 id24 id23 id22 id21 id20 - read parameter 0 1 - 1 1 0 1 1 1 0 0 (dch) read id3 1 1 - - - - - - - - - - dummy read rdid3 7.1.40 1 1 - id37 id36 id35 id34 id33 id32 id31 id30 - read parameter www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 90 confidential leadis technology table 7.1.3 instruction code (extended code set) ?-?: don?t care instruction refer dc w rb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 - 1 0 1 1 0 0 0 0 (b0h) set display interface mode 1 1 - - - - - - - if1 if0 - data transfer mode set ifmode 7.1.41 1 1 - - - dw - dp ep hsp vsp - rgb i/f data width & clock polarity set 0 1 - 1 0 1 1 0 0 0 1 (b1h) display clock set 1 1 - ha7 ha 6 ha 5 ha 4 ha 3 ha 2 ha 1 ha 0 - number of clocks during 1h (full-color) 1 1 - - - bpa5 bpa4 bpa3 bpa2 bpa1 bpa0 - number of vertical back porches (full-color) 1 1 - - - fpa5 fpa4 fpa3 fpa2 fpa1 fpa0 - number of vertical front porches (full-color) 1 1 - hb7 hb 6 hb 5 hb 4 hb 3 hb 2 hb 1 hb 0 - number of clocks during 1h (8-color) 1 1 - - - bpb5 bpb4 bpb3 bpb2 bpb1 bpb0 - number of vertical back porches (8-color) disclk 7.1.42 1 1 - - - fpb5 fpb4 fpb3 fpb2 fpb1 fpb0 - number of vertical front porches (8-color) 0 1 - 1 0 1 1 0 0 1 0 (b2h) display inversion control 1 1 - 0 0 0 0 - nla2 nla1 nla0 - line inversion (full color) invctr 7.1.43 1 1 - 0 0 0 0 - nlb2 nlb1 nlb0 - line inversion (8-color) 0 1 - 1 1 0 0 0 0 0 0 (c0h) regulator control regctr 7.1.44 1 1 - - vr2 vr1 vr0 - vs2 vs1 vs0 - vr/vs regulator output voltage control 0 1 - 1 1 0 0 0 0 0 1 (c1h) vcoml/vcomh voltage control 1 1 - - - vclc5 vclc4 vclc3 vclc2 vclc1 vclc0 - -2.5v ~ +0.5v (50mv step) vcomctr 7.1.45 1 1 - - - vchc5 vchc4 vchc3 vchc2 vchc1 vchc0 - +2.5v ~ +5.5v (50mv step) gamctr1 7.1.46 0 1 - 1 1 0 0 1 0 0 0 (c8h) set gamma correction characteristics 1 1 - - - gs102 gs101 gs100 gs112 gs111 gs110 - gamma adjustment . 1 1 - - - gs122 gs121 gs120 gs132 gs131 gs130 - gamma adjustment . 1 1 - - - gs142 gs141 gs140 gs152 gs151 gs150 - gamma adjustment . 1 1 - - - gs162 gs161 gs160 gs172 gs171 gs170 - gamma adjustment . gamctr2 7.1.47 0 1 - 1 1 0 0 1 0 0 1 (c9h) set gamma correction characteristics 1 1 - - - gs202 gs201 gs200 gs212 gs211 gs210 - gamma adjustment . 1 1 - - - gs222 gs221 gs220 gs232 gs231 gs230 - gamma adjustment . 1 1 - - - gs242 gs241 gs240 gs252 gs251 gs250 - gamma adjustment . 1 1 - - - gs262 gs261 gs260 gs272 gs271 gs270 - gamma adjustment . gamctr3 7.1.48 0 1 - 1 1 0 0 1 0 1 0 (cah) set gamma correction characteristics 1 1 - - - gs302 gs301 gs300 gs312 gs311 gs310 - gamma adjustment . 1 1 - - - gs322 gs321 gs320 gs332 gs331 gs330 - gamma adjustment . 1 1 - - - gs342 gs341 gs340 gs352 gs351 gs350 - gamma adjustment . 1 1 - - - gs362 gs361 gs360 gs372 gs371 gs370 - gamma adjustment . gamctr4 7.1.49 0 1 - 1 1 0 0 1 0 1 1 (cbh) set gamma correction characteristics 1 1 - - - gs402 gs401 gs400 gs412 gs411 gs410 - gamma adjustment . 1 1 - - - gs422 gs421 gs420 gs432 gs431 gs430 - gamma adjustment . 1 1 - - - gs442 gs441 gs440 gs452 gs451 gs450 - gamma adjustment . 1 1 - - - gs462 gs461 gs460 gs472 gs471 gs470 - gamma adjustment . www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 91 confidential leadis technology table 7.1.4 instruction code (extended code set, continued) ?-?: don?t care note: 1) after the h/w reset by resb pin or s/w reset by swreset command, each internal register becomes default state (refer ?reset table? section) 2) before command d1(eper) , supply 22v to the me_cmp for eeprom erase . 3) before command d2(eppgm), supply 8.5v to the me_cmp for eeprom program . 4) to use extended code set, the tgs pad should be connected to vss. extended code set is just used for module test. if tgs pad is not connected to vss, all the extended code set will be ignored and regarded as nop (00h) command. 5) undefined commands are treated as nop (00 h) command. 6) commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ml parameter only), 37h, 38h and 39h are updated during v-sync when module is in sleep out mode to avoid abnormal visual effects. during sleep in mode, these commands are updated immediately. read status (09h), read display power mode (0a h ), read display madctl (0b h ), read display pixel format (0c h ), read display image mode (0d h ), read display signal mode (0e h ) and read display self diagnostic result (0f h ) of these commands of these commands is updated immediately both in sleep in mode and sleep out mode. instructi on refer dc wrb rdb d17 -8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) function 0 1 - 1 1 0 1 0 0 0 0 (d0h) write id2,vcom offset for eeprom program 1 1 - - - - - - vcof82 vcof81 vcof80 - vcom middle voltage trimming in 8color 1 1 - - vcof5 vcof4 vcof3 vcof2 vcof1 vcof0 vcom middle voltage trimming eppgmdb 7.1.50 1 1 id26 id25 id24 id23 id22 id21 id20 db_sel just id2 [6:0] are stored in eeprom eperase 7.1.51 0 1 - 1 1 0 1 0 0 0 1 (d1h) eeprom erase epprog 7.1.52 0 1 - 1 1 0 1 0 0 1 0 (d2h) eeprom program 0 1 - 1 1 0 1 0 0 1 1 (d3h) eeprom read, verify register set eprdvrf 7.1.53 0 0 0 0 read pgmvf ervf 0 macro read , program verify,erase verify 0 1 - 1 1 0 1 1 0 0 1 (d9h) vcom offset bits read 1 1 - - - - - - - - - - dummy read 1 1 - - - rvcof5 rvcof4 rvcof3 rvcof2 rvcof1 rvcof0 - read parameter rdvcof 7.1.54 1 1 rvcof82 rvcof81 rvcof80 read parameter 0 1 - 1 1 1 0 1 1 1 1 (efh) write led control value 1 1 type - led driver type 1 1 0 adr2 adr1 adr0 db3 db2 db1 db0 - control value for lds8861 ledctrl 7.1.55 1 1 0 per3 per2 per1 per0 step2 step1 step0 - contorl value for pwm output www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 92 confidential leadis technology 7.1.2 nop (00h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) nop 0 1 - 0 0 0 0 0 0 0 0 (00h) parameter no parameter note: ?-? don?t care description this command is empty command. it does not have effect on the display module. however it can be used to terminate ddram data write or read as described in ramwr (memory write), ramrd (memory read) and parameter write commands. restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence n/a s/w reset n/a h/w reset n/a flow chart - www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 93 confidential leadis technology 7.1.3 swreset: software reset (01h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) swreset 0 1 - 0 0 0 0 0 0 0 1 (01h) parameter no parameter note: ?-? don?t care description when the software reset command is written, it causes a software reset. it resets the commands and parameters to their s/w reset default values and all source & gate outputs are set to vss (display off). (see defaul t tables in each command description) note: the ddram contents are not affected by this command. restriction it will be necessary to wait 5msec before sending new command following software reset. the display module loads all display supplier?s fact ory default values to the registers during 5msec. if software reset is applied during sleep out mode, it will be necessary to wait 120msec before sending sleep out command. software reset command cannot be sent during sleep out sequence. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence n/a s/w reset n/a h/w reset n/a flow chart swreset display whole blank screen set commands to s/w default value slee p in mode red and blue parameter dis p la y action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 94 confidential leadis technology 7.1.4 rddid: read display id (04h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddid 0 1 - 0 0 0 0 0 1 0 0 (04h) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 - 3 rd parameter 1 1 - id27 id26 id25 id24 id23 id22 id21 id20 - 4 th parameter 1 1 - id37 id36 id35 id34 id33 id32 id31 id30 - note: ?-? don?t care description this read byte returns 24-bit display identification information. the 1 st parameter is dummy data the 2 nd parameter (id17 to id10): lcd module?s manufacturer id. the 3 rd parameter (id27 to id20): lcd module/driver version id the 4 th parameter (id37 to ud30): lcd module/driver id. note: commands rdid1/2/3(dah, dbh, dch) read data correspond to the parameters 2,3,4 of the command 04h, respectively. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status id1 id2 id3 power on sequence not fixed not fixed not fixed s/w reset not fixed not fixed not fixed h/w reset not fixed not fixed not fixed flow chart legend command parameter dis p la y action mode sequential transfer host driver serial i/f mode rddid (04h) dumm y clock send id1 [ 7:0 ] send id2 [ 7:0 ] send id3 [ 7:0 ] rddid (04h) parallel i/f mode dumm y read send id1 [ 7:0 ] send id2 [ 7:0 ] send id3 [ 7:0 ] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 95 confidential leadis technology 7.1.5 rddst: read display status (09h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddst 0 1 - 0 0 0 0 1 0 0 1 (09h) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - st31 st30 st29 st28 st27 st26 st25 st24 - 3 rd parameter 1 1 - st23 st22 st21 st20 st19 st18 st17 st16 - 4 th parameter 1 1 - st15 st14 st13 st12 st11 st10 st9 st8 - 5 th parameter 1 1 - st7 st6 st5 st4 st3 st2 st1 st0 - note: ?-? don?t care description this command indicates the current status of the display as described in the table below: bit description value st31 booster voltage status ?1?=booster on, ?0?=off st30 row address order (my) ?1?=decrement, ?0?=increment st29 column address order (mx) ?1?=decrement, ?0?=increment st28 row/column exchange (mv) ?1?= row/column exchange (mv=1) ?0?= normal (mv=0) st27 scan address order (ml) ?1?=decrement, ?0?=increment st26 rgb/bgr order (rgb) ?1?=bgr, ?0?=rgb st25 not used ?0? st24 not used ?0? st23 not used ?0? st22 st21 st20 interface colour pixel format definition ?110? = 18-bit / pixel (666 mode) ?111? = 24-bit / pixel (888 mode) st19 idle mode on/off ?1? = on, ?0? = off st18 partial mode on/off ?1? = on, ?0? = off st17 sleep in/out ?1? = out, ?0? = in st16 display normal mode on/off ?1? = normal display, ?0? = partial display st15 vertical scrolling status ?1? = scroll on, ?0? = scroll off st14 not used ?0? st13 inversion status ?1? = on, ?0? = off st12 all pixels on (not used) ?0? st11 all pixels off (not used) ?0? st10 display on/off ?1? = on, ?0? = off st9 tearing effect line on/off ?1? = on, ?0? = off st8 st7 st6 gamma curve selection ?000? = gc0, ?001? = gc1, ?010? = gc2, ?011? = gc3 ?100?~?111?:not used st5 tearing effect line mode ?0? = mode1, ?1? = mode2 st4 not used ?0? st3 not used ?0? st2 not used ?0? st1 not used ?0? st0 not used ?0? www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 96 confidential leadis technology restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (st31 to st0): power on sequence 0000 0000_0111 0001_0000 0000_0000 0000 s/w reset 0xxx xx00_0xxx 0001_0000 0000_0000 0000 h/w reset 0000 0000_0111 0001_0000 0000_0000 0000 flow chart legend command parameter dis p la y action mode sequential transfer serial i/f mode rddst (09h) host driver parallel i/f mode rddst (09h) dumm y clock send st [ 31:24 ] send st [ 23:16 ] send st [ 15:8 ] send st [ 7:0 ] dumm y read send st [ 31:24 ] send st [ 23:16 ] send st [ 15:8 ] send st [ 7:0 ] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 97 confidential leadis technology 7.1.6 rddpm: read display power mode (0ah) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddpm 0 1 - 0 0 0 0 1 0 1 0 (0ah) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 - note: ?-? don?t care description this command indicates the current status of the display as described in the table below: bit description value d7 booster voltage status ?1?=booster on, ?0?=booster off d6 idle mode on/off ?1? = idle mode on, ?0? = idle mode off d5 partial mode on/off ?1? = partial mode on, ?0? = partial mode off d4 sleep in/out ?1? = sleep out, ?0? = sleep in d3 display normal mode on/off ?1? = normal display, ?0? = partial display d2 display on/off ?1? = display on, ?0? = display off d1 not used ?0? d0 not used ?0? restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 0000_1000 (08h) s/w reset 0000_1000 (08h) h/w reset 0000_1000 (08h) flow chart legend command parameter dis p la y action mode sequential transfer serial i/f mode rddpm (0ah) host driver parallel i/f mode rddpm (0ah) send d [ 7:0 ] dumm y read send d [ 7:0 ] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 98 confidential leadis technology 7.1.7 rddmadctr: read display madctr (0bh) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddmadctr 0 1 - 0 0 0 0 1 0 1 1 (0bh) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 - note: ?-? don?t care description this command indicates the current status of the display as described in the table below: bit description value d7 row address order ?1?=decrement, ?0?=increment d6 column address order ?1?=decrement, ?0?=increment d5 row/column order (mv) ?1?= row/column exchange (mv=1) ?0?= normal (mv=0) d4 scan address order ?1?=decrement, ?0?=increment d3 rgb/bgr order ?1?=bgr, ?0?=rgb d2 not used ?0? d1 not used ?0? d0 not used ?0? restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 0000_0000 (00h) s/w reset no change h/w reset 0000_0000 (00h) flow chart legend command parameter dis p la y action mode sequential transfer serial i/f mode rddmadctr (0bh) host driver parallel i/f mode rddmadctr (0bh) send d [ 7:0 ] dumm y read send d [ 7:0 ] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 99 confidential leadis technology 7.1.8 rddcolmod: read display pixel format (0ch) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddcolmod 0 1 - 0 0 0 0 1 1 0 0 (0ch) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 - note: ?-? don?t care description this command indicates the current status of the display as described in the table below: bit description value d7 ?0? (not used) d6 ?0? (not used) d5 ?0? (not used) d4 rgb interface color format ?0? (not used) d3 ?0? d2 d1 d0 control interface color format ?111?=24 bit/pixel ?011?=12 bit/pixel ?101?=16 bit/pixel ?110?=18 bit/pixel restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 0000_0111 (24 bit/pixel) s/w reset no change h/w reset 0000_0111 (24 bit/pixel) flow chart legend command parameter dis p la y action mode sequential transfer serial i/f mode rddcolmod (0ch) host driver parallel i/f mode rddcolmod (0ch) send d [ 7:0 ] dumm y read send d [ 7:0 ] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 100 confidential leadis technology 7.1.9 rddim: read display image mode (0dh) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddim 0 1 - 0 0 0 0 1 1 0 1 (0dh) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 - note: ?-? don?t care description this command indicates the current status of the display as described in the table below: bit description value d7 vertical scrolling on/off ?0? (not used) d6 horizontal scrolling on/off ?0? (not used) d5 inversion on/off ?1? = inversion is on, ?0? = inversion is off d4 all pixels on ?0? (not used) d3 all pixels off ?0? (not used) d2 d1 d0 gamma curve selection ?000? = gc0, ?001? = gc1 ?010? = gc2, ?011? = gc3 ?100? to ?111? = not defined restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 0000_0000 (00h) s/w reset 0000_0000 (00h) h/w reset 0000_0000 (00h) flow chart legend command parameter dis p la y action mode sequential transfer serial i/f mode rddim (0dh) host driver parallel i/f mode rddim (0dh) send d [ 7:0 ] dumm y read send d [ 7:0 ] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 101 confidential leadis technology 7.1.10 rddsm: read display signal mode (0eh) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddsm 0 1 - 0 0 0 0 1 1 1 0 (0eh) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 - note: ?-? don?t care description this command indicates the current status of the display as described in the table below: bit description value d7 tearing effect line on/off ?1? = on, ?0? = off d6 tearing effect line mode ?0? = mode1, ?1? = mode2 d5 horizontal sync. (rgb i/f) on/off ?0? d4 vertical sync. (rgb i/f) on/off ?0? d3 pixel clock (dck, rgb i/f) on/off ?0? d2 data enable (enable, rgb i/f) on/off ?0? d1 not used ?0? d0 not used ?0? restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 0000_0000 (00h) s/w reset 0000_0000 (00h) h/w reset 0000_0000 (00h) flow chart legend command parameter dis p la y action mode sequential transfer serial i/f mode rddsm (0eh) host driver parallel i/f mode rddsm (0eh) send d [ 7:0 ] dumm y read send d [ 7:0 ] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 102 confidential leadis technology 7.1.11 rddsdr: read display self-diagnostic result (0fh) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rddsdr 0 1 - 0 0 0 0 1 1 1 1 (0fh) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - d7 d6 d5 d4 d3 d2 d1 d0 - note: ?-? don?t care description this command indicates the current status of the display as described in the table below: bit description value d7 register loading detection d6 functionality detection d5 chip attachment detection d4 display glass break detection refer section 5.14 d3 not used ?0? d2 not used ?0? d1 not used ?0? d0 not used ?0? restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (d7 to d0) power on sequence 0000_0000 (00h) s/w reset 0000_0000 (00h) h/w reset 0000_0000 (00h) flow chart legend command parameter dis p la y action mode sequential transfer serial i/f mode rddsdr (0fh) host driver parallel i/f mode rddsdr (0fh) send d [ 7:0 ] dumm y read send d [ 7:0 ] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 103 confidential leadis technology 7.1.12 slpin: sleep in (10h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) slpin 0 1 - 0 0 0 1 0 0 0 0 (10h) parameter no parameter note: ?-? don?t care description this command causes the lcd module to enter the minimum power consumption mode. in this mode the dc/dc converter is stopped, internal display oscillator is stopped, and panel scanning is stopped. mpu interface and memory are still working and the memory keeps its contents restriction this command has no effect when module is already in sleep in mode. sleep in mode can only be exit by the sleep out command (11h). it will be necessary to wait 5msec before sending nex t command, this is to allow time for the supply voltages and clock circuits to stabilize. it will be necessary to wait 120msec after sending sleep out command (when in sleep in mode) before sleep in command can be sent. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence sleep in mode s/w reset sleep in mode h/w reset sleep in mode source/gate output stop memory scan operation stop internal oscillator stop dc/dc converter discharge blank display www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 104 confidential leadis technology flow chart it takes about 120 msec to get into sleep in mode (booster off state) after slpin command issued. the results of booster off can be check by rddst (09h) command bit31. splin display whole blank screen (automatic no effect to disp on/off command) drain charge from lcd panel stop dc/dc converter stop internal oscillator sleep in mode legend command parameter dis p la y action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 105 confidential leadis technology 7.1.13 slpout: sleep out (11h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) slpout 0 1 - 0 0 0 1 0 0 0 1 (11h) parameter no parameter note: ?-? don?t care description this command turns off sleep mode. in this mode the dc/dc converter is enabled, internal display oscillator is started, and panel scanning is started. restriction this command has no effect when module is already in sleep out mode. sleep out mode can only be exit by the sleep in command (10h). it will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to be stabilized. LDS285 loads all default values of extended and test command to the registers during this 5msec and there cannot be any abnormal visual effect on the display image if those default and register values are same when this load is done and then the LDS285 is already sleep out ?mode. LDS285 is doing self-diagnostic functions during this 5msec. see also section 5.14. it will be necessary to wait 120msec after sending sleep in command (when in sleep out mode) before sleep out command can be sent register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence sleep in mode s/w reset sleep in mode h/w reset sleep in mode stop start stop source/gate output memory contents memory scan operation (if dispon 29h is set) internal oscillator dc/dc converter 0v blank www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 106 confidential leadis technology flow chart it takes 120msec to become sleep out mode (booster on mode) after slpout command issued. the results of booster on can be checked by rddst (09h) command bit31. legend command parameter dis p la y action mode sequential transfer slpout charge offset voltage for lcd panel sleep out mode start internal oscillator start dc-dc converter display whole blank screen (automatic no effect to disp on/off commands) displa y memory contents in accordance with the current command table settings www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 107 confidential leadis technology 7.1.14 ptlon: partial display mode on (12h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ptlon 0 1 - 0 0 0 1 0 0 1 0 (12h) parameter no parameter note: ?-? don?t care description this command turns on partial mode. the partial mode window is described by the partial area command (30 h ) to leave partial mode, the normal displa y mode on command (13h) should be written. there is no abnormal visual effect during mode change between normal mode on <-> partial mode on. restriction this command has no effect when partial mode is active. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence normal mode on s/w reset normal mode on h/w reset normal mode on flow chart see partial area (30h) www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 108 confidential leadis technology 7.1.15 noron: normal display mode on (13h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) noron 0 1 - 0 0 0 1 0 0 1 1 (13h) parameter no parameter note: ?-? don?t care description this command returns the display to normal mode. normal display mode on means partial mode off. there is no abnormal visual effect during mode change from normal mode on <-> partial mode on. restriction this command has no effect when normal display mode is active. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence normal mode on s/w reset normal mode on h/w reset normal mode on flow chart see partial area and vertical scrolling definition descriptions for details of when to use this command www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 109 confidential leadis technology 7.1.16 invoff: display inversion off (20h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) invoff 0 1 - 0 0 1 0 0 0 0 0 (20h) parameter no parameter note: ?-? don?t care description this command is used to recover from display inversion mode. this command makes no change of contents of frame memory. this command does not change any other status. restriction this command has no effect when module is already inversion off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display inversion off s/w reset display inversion off h/w reset display inversion off flow chart invoff display inversion off mode display inversion on mode legend command parameter dis p la y action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 110 confidential leadis technology 7.1.17 invon: display inversion on (21h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) invon 0 1 - 0 0 1 0 0 0 0 1 (21h) parameter no parameter note: ?-? don?t care description this command is used to enter into display inversion mode this command makes no change of contents of frame memory. every bit is inverted form the frame memory to the display. this command does not change any other status. restriction this command has no effect when module is already inversion on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display inversion off s/w reset display inversion off h/w reset display inversion off flow chart invon display inversion on mode display inversion off mode legend command parameter dis p la y action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 111 confidential leadis technology 7.1.18 gamset: gamma set (26h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) invon 0 1 - 0 0 1 0 0 1 0 1 (26h) parameter 1 1 - gc7 gc6 gc5 gc4 gc3 gc2 gc1 gc0 - note: ?-? don?t care description this command is used to select the desired gamma curve for the current display. a maximum of 4 curves can be selected. the curves are defined in fig 5.9.3 the curve is selected by setting the appropriate bit in the parameter as described in the table. gc [7:0] parameter curve selected 01h gc0 gamma curve 1 02h gc1 gamma curve 2 04h gc2 gamma curve 3 08h gc3 gamma curve 4 note: all other values are undefined. restriction values of gc [7:0] not shown in table above are invalid and will not change the current selected gamma curve until valid is received . register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 01h s/w reset 01h h/w reset 01h flow chart legend command parameter dis p la y action mode sequential transfer gamset gc [7:0] new gamma curve loaded www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 112 confidential leadis technology 7.1.19 dispoff: display off (28h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) dispoff 0 1 - 0 0 1 0 1 0 0 0 (28h) parameter no parameter note: ?-? don?t care description this command is used to enter into display off mode. in this mode, the output from ddram is disabled and blank page is inserted for two frames. this command makes no change of contents of ddram. this command does not change any other status. there will be no abnormal visible effect on the display. exit from this command by display on (29h) restriction this command has no effect when module is already in display off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display off s/w reset display off h/w reset display off flow chart legend command parameter dis p la y action mode sequential transfer (example) memory display dispoff display on mode display off mode display whole blank screen for 2 frames (automatic no effect to disp on/off www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 113 confidential leadis technology 7.1.20 dispon: display on (29h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) dispon 0 1 - 0 0 1 0 1 0 0 1 (29h) parameter no parameter note: ?-? don?t care description this command is used to recover from display off mode. output from the ddram is enabled. this command makes no change of contents of ddram. this command does not change any other status. restriction this command has no effect when module is already in display on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display off s/w reset display off h/w reset display off flow chart dispon display off mode display on mode legend command parameter display action mode sequential transfer (example) memory display www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 114 confidential leadis technology 7.1.21 caset: column address set (2ah) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) caset 0 1 - 0 0 1 0 1 0 1 0 (2ah) 1 st parameter 1 1 - xs15 xs14 xs13 xs12 xs11 xs10 xs9 xs8 - 2 nd parameter 1 1 - xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 - 3 rd parameter 1 1 - xe15 xe14 xe13 xe12 xe11 xe10 xe9 xe8 - 4 th parameter 1 1 - xe7 xe6 xe5 xe4 xe3 xe2 xe1 xe0 - note: ?-? don?t care description this command is used to define area of ddram where mpu can access. this command makes no change on the other driver status. the value of xs [15:0] and xe [15:0] are referred when ramwr command comes. each value represents one column line in the ddram. (example) restriction xs [15:0] always must be equal to or less than xe [15:0] when xs [15:0] or xe [15:0] is greater than maximu m address like below, data of out of range will be ignored. (parameter range: 0 xs [15:0] xe [15:0] 239 (00efh)): mv=?0? (parameter range: 0 xs [15:0] xe [15:0] 319 (013fh)): mv=?1? (about mv register, refer section 6.1.30 ( row / column exchange ) ) register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status xs [15:0] xe [15:0] (mv=0) xe [15:0] (mv=1) power on sequence 0000h 00efh(239d) s/w reset 0000h 00efh(239d) 013fh(319d) h/w reset 0000h 00efh(239d) xs [ 15:0 ] xe [ 15:0 ] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 115 confidential leadis technology flow chart legend command parameter display action mode sequential transfer if needed caset 1 st & 2 nd parameter xs [15:0] 3 rd & 4 th parameter xe [15:0] raset ramwr image data d1[15:0],d2[15:0] ?..dn [ 15:0 ] any command 1 st & 2 nd parameter ys [15:0] 3 rd & 4 th parameter ye [15:0] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 116 confidential leadis technology 7.1.22 raset: row address set (2bh) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) raset 0 1 - 0 0 1 0 1 0 1 1 (2bh) 1 st parameter 1 1 - ys15 ys14 ys13 ys12 ys11 ys10 ys9 ys8 - 2 nd parameter 1 1 - ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 - 3 rd parameter 1 1 - ye15 ye14 ye13 ye12 ye11 ye10 ye9 ye8 - 4 th parameter 1 1 - ye7 ye6 ye5 ye4 ye3 ye2 ye1 ye0 - note: ?-? don?t care description this command is used to define area of ddram where mpu can access. this command makes no change on the other driver status. the value of ys [15:0] and ye [15:0] are referred when ramwr command comes. each value represents one column line in the ddram. (example) restriction ys [15:0] always must be equal to or less than ye [15:0] when ys [15:0] or ye [15:0] are greater than maximum ro w address like below, data of out of range will be ignored. (parameter range: 0 ys [15:0] ye [15:0] 319 (013fh)): mv=?0? (parameter range: 0 ys [15:0] ye [15:0] 239 (00efh)): mv=?1? (about mv register, refer section 6.1.30 ( row / column exchange ) ) register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status ys [15:0] ye [15:0] (mv=0) ye [15:0] (mv=1) power on sequence 0000h 013fh(319d) s/w reset 0000h 013fh(319d) 00efh (239d) h/w reset 0000h 013fh(319d) ys [ 15:0 ] ye [ 15:0 ] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 117 confidential leadis technology flow chart if needed if nee ded legend command parameter display action mode sequential transfer caset raset ramwr image data d1[15:0],d2[15:0] ?..dn [ 15:0 ] any command 1 st & 2 nd parameter ys [15:0] 3 rd & 4 th parameter ye [15:0] 1 st & 2 nd parameter xs [15:0] 3 rd & 4 th parameter xe [15:0] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 118 confidential leadis technology 7.1.23 ramwr: memory write (2ch) inst / para dc wrb rdb d15-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ramwr 0 1 - 0 0 1 0 1 1 0 0 (2ch) data write 1 1 d15-8 d7 d6 d5 d4 d3 d2 d1 d0 - : : : : : : : : : : : : : : data write 1 1 d15-8 d7 d6 d5 d4 d3 d2 d1 d0 - note: ?-? don?t care description this command is used to transfer data mpu to ddram. this command makes no change to the other driver status. when this command is accepted, the column register and the row register are reset to the start column/start row positions. the start column/start row positions are different in accordance with madctr setting. (see 5.2.3) then d [15:0] is stored in ddram and the column register and the row register increment as in fig 5.2.4 . sending any other command can stop frame write. restriction in all color modes, there is no restriction on length of parameters. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence contents of memory is set randomly s/w reset contents of memory is not cleared h/w reset contents of memory is not cleared flow chart legend command parameter display action mode sequential transfer image data d1[15:0],d2[15:0], ?.,dn[15:0 ramwr any command www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 119 confidential leadis technology 7.1.24 ramrd: memory read (2eh) inst / para dc wrb rdb d15-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ramrd 0 1 - 0 0 1 0 1 1 1 0 (2eh) dummy read 1 1 - - - - - - - - - - data read 1 1 d15-8 d7 d6 d5 d4 d3 d2 d1 d0 - : : : : : : : : : : : : : : data read 1 1 d15-8 d7 d6 d5 d4 d3 d2 d1 d0 - note: ?-? don?t care description this command is used to transfer data from ddram to mpu. this command makes no change to the other driver status. when this command is accepted, the column regist er and the row register are reset to the start column/start row positions. the start column/start row positions are diff erent in accordance with madctr setting. (see section 5.2.3) then d[15:0] is read back from the ddram and the column register and the row register increment as in fig. 5.2.4. frame read can be canceled by sending any other command. restriction in all color modes, there is no restriction on length of parameters. note ? memory read is only possible via the parallel interface . register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence contents of memory is set randomly s/w reset contents of memory is not cleared h/w reset contents of memory is not cleared flow chart ramrd dummy image data d1[15:0],d2[15:0] ?..dn [ 15:0 ] any command legend command parameter display action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 120 confidential leadis technology 7.1.25 ptlar: partial area (30h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ptlar 0 1 - 0 0 1 1 0 0 0 0 (30h) 1 st parameter 1 1 - psl15 psl14 psl13 psl12 psl11 psl10 psl9 psl8 - 2 nd parameter 1 1 - psl7 psl6 psl5 psl4 psl3 psl2 psl1 psl0 - 3 rd parameter 1 1 - pel15 pel14 pel13 pel12 pel11 pel10 pel9 pel8 - 4 th parameter 1 1 - pel7 pel6 pel5 pel4 pel3 pel2 pel1 pel0 - note: ?-? don?t care description this command defines the partial mode?s display area. there are 4 parameters associated with this command, the first defines the start row (psl) and the second the end row (pel), as illustrated in the figures below. psl and pel refer to the ddram row address counter. if end row > start row when madctl ml=0: if end row > start row when madctl ml=1: if end row < start row when madctl ml=0: if end row = start row then the partial area will be one row deep. restriction psl[15:0] and pel[15:0] should have below range (parameter range: 0 psl[15:0], pel[15:0] 319 (013fh) ) psl [15:0] pel [15:0] start row end row partial display area non-displaying area non-displaying area pel [15:0] psl [15:0] end row start row partial display area non-displaying area non-displaying area non-displaying area non-displaying area pel [15:0] psl [15:0] end row start row partial display area non-displaying area www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 121 confidential leadis technology register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status psl [15:0] pel [15:0] power on sequence 0000h 013fh s/w reset 0000h 013fh h/w reset 0000h 013fh flow chart 1. to enter partial mode 2. to exit partial mode legend command parameter display action mode sequential transfer ptlar psl [15:0] pel [15:0] ptlon partial mode partial mode dispoff noron partial mode off ramrw image data d1[15:0],d2[15:0] ?..dn [ 15:0 ] dispon optional to prevent tearing effect image display www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 122 confidential leadis technology 7.1.26 teoff: tearing effect line off (34h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) teoff 0 1 - 0 0 1 1 0 1 0 0 (34h) parameter no parameter note: ?-? don?t care description this command is used to turn off (active low) the tearing effect output signal from the te signal line. restriction this command has no effect when tearing effect output is already off. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence off s/w reset off h/w reset off flow chart teoff te line out p ut off te line out p ut on legend command parameter dis p la y action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 123 confidential leadis technology 7.1.27 teon: tearing effect line on (35h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) teon 0 1 - 0 0 1 1 0 1 0 1 (35h) parameter 1 1 - - - - - - - - m - note: ?-? don?t care description this command is used to turn on the tearing effect output signal from the te signal line. this output is not affected by changing madctr bit ml. the tearing effect line on has one parameter, which describes the mode of the tearing effect output line. (?-?=don?t care). when m=0: the tearing effect output line consists of v-blanking information only. vertical time scale when m=1: the tearing effect output line consists of both v-blanking and h-blinking information. vertical time scale see section 5.2.7 for more information. note: during sleep in mode with tearing effect line on, tearing effect output pin will be active low. restriction this command has no effect when tearing effect output is already off. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence tearing effect off & m=0 s/w reset tearing effect off & m=0 h/w reset tearing effect off & m=0 flow chart legend command parameter dis p la y action mode sequential transfer teon te line out p ut on te line out p ut off te mode parameter (m) t vdl t vdh t vdl t vdh www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 124 confidential leadis technology 7.1.28 madctr: memory data access control (36h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) madctr 0 1 - 0 0 1 1 0 1 1 0 (36h) parameter 1 1 - my mx mv ml rgb - - - - note: ?-? don?t care description this command defines read/write scanning direction of ddram. this command makes no change on the other driver status. bit assignment bit name description my row address order mx column address order mv row/column exchange these 3bits controls mpu to memory write/read direction. (see section 5.2.3) ml scan address order lcd refresh direction control rgb rgb-bgr order color selector swit ch control. ddram must be updated after the rgb bit change. (0=rgb color filter panel, 1=bgr color filter panel) restriction d2, d1 and d0 of the 1 st parameter are set to ?000?internally. ml: scan address order ml=?0? ml=?1? memory display sent first sent 2nd sent 3rd sent last memory display sent first sent 2nd sent 3rd sent last rgb: rgb-bgr order rgb=?0? rgb=?1? r g b r g b sig1 sig128 driver ic lcd panel r g b r g b r g b r g b r g b r g b sig1 sig128 sig2 sig2 r g b r g b sig1 sig128 driver ic lcd panel b g r b g r b g r b g r b g r b g r sig1 sig128 sig2 sig2 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 125 confidential leadis technology register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence my=0,mx=0,mv=0,ml=0,rgb=0 s/w reset no change h/w reset my=0,mx=0,mv=0,ml=0,rgb=0 flow chart madctr 1 st parameter (my, mx, mv, ml, rgb) legend command parameter dis p la y action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 126 confidential leadis technology 7.1.29 idmoff: idle mode off (38h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) idmoff 0 1 - 0 0 1 1 1 0 0 0 (38h) parameter no parameter note: ?-? don?t care description this command is used to recover from idle mode on. there will be no abnormal visible effect on the display mode change transition. in the idle off mode, 1. lcd can display maximum 4k, 65k, 262k or 16m-colors. 2. normal frame frequency is applied. restriction this command has no effect when module is already in idle off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence idle mode off s/w reset idle mode off h/w reset idle mode off flow chart idle mode on idmoff idle mode off legend command parameter dis p la y action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 127 confidential leadis technology 7.1.30 idmon: idle mode on (39h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) idmon 0 1 - 0 0 1 1 1 0 0 1 (39h) parameter no parameter note: ?-? don?t care description this command is used to enter into idle mode on. there will be no abnormal visible effect on the display mode change transition. in the idle on mode, 1. color expression is reduced. the primary and the secondary colors using msb of each r,g and b in the ddram, 8 color depth data is displayed. 2. 8-color mode frame frequency is applied. 3. exit from idmon by idle mode off (38h) command (example) memory display ?x?: don?t care color r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 g 7 g 6 g 5 g 4 g 3 g 2 g 1 g 0 b 7 b 6 b 5 b 4 b 3 b 4 b 1 b 0 black 0xxxxxxx 0xxxxxxx 0xxxxxxx blue 0xxxxxxx 0xxxxxxx 1xxxxxxx red 1xxxxxxx 0xxxxxxx 0xxxxxxx magenta 1xxxxxxx 0xxxxxxx 1xxxxxxx green 0xxxxxxx 1xxxxxxx 0xxxxxxx cyan 0xxxxxxx 1xxxxxxx 1xxxxxxx yellow 1xxxxxxx 1xxxxxxx 0xxxxxxx white 1xxxxxxx 1xxxxxxx 1xxxxxxx restriction this command has no effect when module is already in idle on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence idle mode off s/w reset idle mode off h/w reset idle mode off www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 128 confidential leadis technology flow chart idle mode off idmon idle mode on legend command parameter dis p la y action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 129 confidential leadis technology 7.1.31 colmod: interface pixel format (3ah) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) colmod 0 1 - 0 0 1 1 1 0 1 0 (3ah) parameter 1 1 - - rp2 rp1 r p 0 - p 2 p 1 p 0 - note: ?-? don?t care description this command is used to define the format of rgb picture data, which is to be transferred via the mpu(p2-0) & rgb(rp2-0) interface. the formats are shown in the table: interface pixel format p2(rp2) p1(rp1) p0(rp0) not defined 0 0 0 not defined 0 0 1 not defined 0 1 0 not defined 0 1 1 not defined 1 0 0 not defined 1 0 1 18bit/pixel 1 1 0 24bit/pixel 1 1 1 note: in 18 bit/pixel mode, the lsb expansion is applied to transfer data into the ddram. restriction there is no visible effect until the ddram is written to. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default power on sequence 24bit/pixel s/w reset no change h/w reset 24bit/pixel flow chart example: legend command parameter dis p la y action mode sequential transfer 24bit/pixel mode colmod 110 18bit/pixel mode www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 130 confidential leadis technology 7.1.32 wrdisbv : write display brightness (51h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) wrdisbv 0 1 - 0 1 0 1 0 0 0 1 (51h) parameter 1 1 - dbv7 dbv6 dbv5 dbv4 dbv3 dbv2 dbv1 dbv0 - note: ?-? don?t care description this command is used to adjust then brightness value of the display. it should be checked what the relationship between this written value and output brightness of the display is. this relationship is defined on the display module specification. 00h value means the lowest brightness and ffh value means the highest brightness. restriction the display supplier cannot use this command for tuning(e.g. factory tuning. etc), because this command is only for nokia. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default power on sequence ffh s/w reset ffh h/w reset ffh flow chart example: legend command parameter dis p la y action mode sequential transfer current brightness value wrdisbv dbv[7:0] new brightness value www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 131 confidential leadis technology 7.1.33 rddisbv : read display brightness (52h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdddisbv 0 1 - 0 1 0 1 0 0 1 0 (52h) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - dbv7 dbv6 dbv5 dbv4 dbv3 dbv2 dbv1 dbv0 - note: ?-? don?t care description this command returns the brightness value of the display. it should be checked what the relationship between this written value and output brightness of the display is. this relationship is defined on the display module specification. 00h value means the lowest brightness and ffh value means the highest brightness. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default power on sequence ffh s/w reset ffh h/w reset ffh flow chart example: legend command parameter dis p la y action mode sequential transfer serial i/f mode rddisbv[52h] send 2 nd p arameter rddisbv[52h] dumm y read send 2 nd p arameter host driver parallel i/f mode www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 132 confidential leadis technology 7.1.34 wrctrld: write ctrl display (53h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) wrctrld 0 1 - 0 1 0 1 0 0 1 1 (53h) parameter 1 1 - - - bctrl - - bl - - - note: ?-? don?t care description this command is used to control brightness setting. bctrl : brightness controll block on/off. this bit is always used to switch brightness for display . ?0? = off ( brightness registers are 00h ) ?1? = on ( brightness registers are active ) bl : backlight control on/off ?0? = off ( completely turn off backlight circuit : control lines must be low.) ?1? = on restriction the display supplier cannot use this command for tuning(e.g. factory tuning. etc), because this command is of only for nokia. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default power on sequence 00h s/w reset 00h h/w reset 00h flow chart example: legend command parameter dis p la y action mode sequential transfer wrctrld bctrl, bl new control value www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 133 confidential leadis technology 7.1.35 rdctrld : read ctrl value display (54h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdctrld 0 1 - 0 1 0 1 0 1 0 0 (54h) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - - - bctrl - - bl - - - note: ?-? don?t care description this command returns the brightness control value. ( see chapter 7.1.34 wrctrld ) bctrl : brightness controll block on/off. this bit is always used to switch brightness for display . ?0? = off ( brightness registers are 00h ) ?1? = on ( brightness registers are active ) bl : backlight control on/off ?0? = off ( completely turn off backlight circuit : control lines must be low.) ?1? = on restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default power on sequence 00h s/w reset 00h h/w reset 00h flow chart example: legend command parameter dis p la y action mode sequential transfer serial i/f mode rdctrld[54h] send 2 nd p arameter rdctrld[54h] dumm y read send 2 nd p arameter host driver parallel i/f mode www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 134 confidential leadis technology 7.1.36 wrcabc: write content adaptive brightness (55h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) wrctrld 0 1 - 0 1 0 1 0 0 1 1 (53h) parameter 1 1 - - - - - - - c 1 c 0 - note: ?-? don?t care description this command is used to set parameters for image content based adaptive brightness control functionality. there is possible to use 4 different modes for content adaptive image functionality, which are difined on a table below c1 c0 function note 0 0 off 0 1 user interface image 1 0 still picture 1 1 moving image restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default power on sequence 00h s/w reset 00h h/w reset 00h flow chart example: legend command parameter dis p la y action mode sequential transfer wrcabc c1,c0 new adaptive image www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 135 confidential leadis technology 7.1.37 rdcabc : read content adaptive brightness (56h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdcabc 0 1 - 0 1 0 1 0 1 1 0 (56h) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - - - - - - - c1 c0 - note: ?-? don?t care description this command is used to read the settings for image content based adaptive brightness control functionality. there is possible to use 4 different modes for content adaptive image functionality, which are difined on a table below c1 c0 function note 0 0 off 0 1 user interface image 1 0 still picture 1 1 moving image restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default power on sequence 00h s/w reset 00h h/w reset 00h flow chart example: legend command parameter dis p la y action mode sequential transfer serial i/f mode rdcabc[56h] send 2 nd p arameter rdcabc[56h] dumm y read send 2 nd p arameter host driver parallel i/f mode www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 136 confidential leadis technology 7.1.38 rdid1: read id1 value (dah) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdid1 0 1 - 1 1 0 1 1 0 1 0 (dah) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - id17 id16 id15 id14 id13 id12 id11 id10 - note: ?-? don?t care description this read byte returns 8-bit lcd module?s manufacturer id the 1 st parameter is dummy data the 2 nd parameter (id17 to id10): lcd module?s manufacturer id. note: see command rddid (04h), 2 nd parameter. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence not fixed s/w reset not fixed h/w reset not fixed flow chart legend command parameter dis p la y action mode sequential transfer serial i/f mode rdid1 (dah) send 2 nd p arameter rdid1 (dah) dumm y read send 2 nd p arameter host driver parallel i/f mode www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 137 confidential leadis technology 7.1.39 rdid2: read id2 value (dbh) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdid2 0 1 - 1 1 0 1 1 0 1 1 (dbh) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - 1 id26 id25 id24 id23 id22 id21 id20 - note: ?-? don?t care description this read byte returns 8-bit lcd module/driver version id the 1 st parameter is dummy data the 2 nd parameter (id26 to id20): lcd module/driver version id parameter range: id=80h to ffh note: see command rddid (04h), 3 rd parameter. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence not fixed s/w reset not fixed h/w reset not fixed flow chart legend command parameter dis p la y action mode sequential transfer serial i/f mode rdid2 (dbh) send 2 nd p arameter rdid2 (dbh) dumm y read send 2 nd p arameter host driver parallel i/f mode www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 138 confidential leadis technology 7.1.40 rdid3: read id3 value (dch) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdid3 0 1 - 1 1 0 1 1 1 0 0 (dch) dummy read 1 1 - - - - - - - - - - 2 nd parameter 1 1 - id37 id36 id35 id34 id33 id32 id31 id30 - note: ?-? don?t care description this read byte returns 8-bit lcd module/driver id. the 1 st parameter is dummy data the 2 nd parameter (id37 to id30): lcd module/driver id. note: see command rddid (04h), 4 th parameter. restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence not fixed s/w reset not fixed h/w reset not fixed flow chart legend command parameter dis p la y action mode sequential transfer serial i/f mode rdid3 (dch) send 2 nd p arameter rdid2 (dch) dumm y read send 2 nd p arameter host driver parallel i/f mode www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 139 confidential leadis technology 7.1.41 ifmode: set display interface mode (b0h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) ifmode 0 1 - 1 0 1 1 0 0 0 0 (b0h) 1 st parameter 1 1 - - - - - - - if1 if0 - 2 nd parameter 1 1 - - - dw - dp ep hsp vsp - note: ?-? don?t care description sets the operation status of the display interface. the setting becomes effective as soon as the command is received. 1 st parameter: interface mode set if1 if0 data transfer mode 0 0 mpu data transfer 0 1 rgb data transfer1 1 0 rgb data transfer2 1 1 rgb data transfer3 2 nd parameter: rgb interface bus width set dw rgb interface data width 0 24-bit (1-transfer for one pixel) 1 8-bit (1-transfer for one pixel) 2 nd parameter: clock polarity set for rgb interface dp: dck polarity set (?0?=data fetched at the rising edge, ?1?=data fetched at the falling edge) ep: enable polarity (?0?= high enable for rgb interface, ?1?=low enable for rgb interface) hsp: hsync polarity (?0?=low level sync clock, ?1?=high level sync clock) vsp: vsync polarity (?0?= low level sync clock, ?1?= high level sync clock) f register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status if [1:0] dw dp/ep/hsp/vsp power on sequence 00 0 0/0/0/0 s/w reset 00 0 0/0/0/0 h/w reset 00 0 0/0/0/0 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 140 confidential leadis technology flow chart ifmode 1 st parameter: if [1:0] 2 nd parameter: dw/ dp/ep/hsp/vsp legend command parameter display action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 141 confidential leadis technology 7.1.42 disclk: display clock set (b1h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) disclk 0 1 - 1 0 1 1 0 0 0 1 (b1h) 1 st parameter 1 1 - ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 - 2 nd parameter 1 1 - - - bpa5 bpa4 bpa3 bpa2 bpa1 bpa0 - 3 rd parameter 1 1 - - - fpa5 fpa4 fpa3 fpa2 fpa1 fpa0 - 4 th parameter 1 1 - hb7 hb6 hb5 hb4 hb3 hb2 hb1 hb0 - 5 th parameter 1 1 - - - bpb5 bpb4 bpb3 bpb2 bpb1 bpb0 - 6 th parameter 1 1 - - - fpb5 fpb4 fpb3 fpb2 fpb1 fpb0 - description display clock condition set. 1 st to 4 th parameter: display clock set for full colour display mode. ha [8:0]: number of clocks during 1h = ha bpa [5:0]: number of lines for vertical back porch fpa [5:0]: number of lines for vertical front porch 5 th to 8 th parameter: display clock set for 8-colour display mode. hb [8:0]: number of clocks during 1h = hb bpb [5:0]: number of lines for vertical back porch fpb [5:0]: number of lines for vertical front porch by using disclk command, frame frequency can be set like below ffra (hz) = 1 / ((number of gate + 1 dummy gate + bpa + fpa) * ((ha+1) * 2usec)) for full colour display mode ffrb (hz) = 1 / ((number of gate + 1 dummy gate + bpb + fpb ) * ((hb+1) * 2usec)) for 8-colour display mode bpa (bpb) and fpa (fpb) are related to the vertical mode te signal pulse width. te (vertical mode, high pulse width) = (bfa + fpa+2) * ((ha+1) * 2usec) for full colour display mode te (vertical mode, high pulse width) = (bfb + fpb+2) * ((hb+1) * 2usec) for 8-colour display mode restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 142 confidential leadis technology default default value status ha [7:0] bpa [5:0] fpa [5:0] hb [7:0] bpb [5:0] fpb [5:0] power on sequence 23d (17h) 16d (10h) 6d (06h) 28d (1ch) 16d (10h) 6d (06h) s/w reset 23d (17h) 16d (10h) 6d (06h) 28d (1ch) 16d (10h) 6d (06h) h/w reset 23d (17h) 16d (10h) 6d (06h) 28d (1ch) 16d (10h) 6d (06h) the default frame frequency (normal mode, 320 gate + 1 dummy gate) = 1/((321+16+6)*(23+1)*2usec) = 60.8hz the default frame frequency (idle mode, 320 gate + 1 dummy gate) = 1/( (321+16+6)*(28+1)*2usec) = 50.2hz vertical te signal high pulse width = (16+6+2)*(23+1)*2usec = 1, 152 usec (for normal mode) = (16+6+2)*(28+1)*2usec = 1,392 usec (for idle mode) flow chart legend command parameter display action mode sequential transfer disclk 1 s t and 2 n d parameter: ha [7:0] 3 rd parameter: bpa [5:0] 4 th parameter: fpa [5:0] 5 th and 6 th parameter: hb [7:0] 7 th parameter: bpb [5:0] 8 th p arameter: fpb [ 5:0 ] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 143 confidential leadis technology 7.1.43 invctr: inversion control (b2h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) invctr 0 1 - 1 0 1 1 0 0 1 0 (b2h) 1 st parameter 1 1 - 0 0 0 0 - nla2 nla1 nla0 - 2 nd parameter 1 1 - 0 0 0 0 - nlb2 nlb1 nlb0 - description display inversion mode set 1 st parameter: for full colour display mode nla2 to nla0: line inversion value set 2 nd parameter: for 8 colour display mode nlb2 to nlb0: line inversion value set nla2 (nlb2) nla1 (nlb1) nla0 (nlb0) inversion 0 0 0 frame inversion 0 0 1 1-line inversion 0 1 0 2-line inversion 0 1 1 3-line inversion 1 0 0 4-line inversion 1 0 1 5-line inversion 1 1 0 6-line inversion 1 1 1 7-line inversion restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status 1 st parameter 2 nd parameter power on sequence 01h 00h s/w reset 01h 00h h/w reset 01h 00h www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 144 confidential leadis technology flow chart invctr 1 st parameter: nla [2:0] 2 nd parameter: nlb [2:0] legend command parameter display action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 145 confidential leadis technology 7.1.44 regctr: regulator control (c0h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) regctr 0 1 - 1 1 0 0 0 0 0 0 (c0h) 1 st parameter 1 1 - - vr2 vr1 vr0 - vs2 vs1 vs0 - description regulator voltage control the 1 st parameter: vr [2:0]: vr regulator output control vs [2:0]: vs regulator output control vr [2:0] vr output vs [2:0] vs/vg output 0 vr = 3.00v 0 vs = 3.00v 1 vr = 3.50v 1 vs = 3.50v 2 vr = 3.75v 2 vs = 3.75v 3 vr = 4.00v 3 vs = 4.00v 4 vr = 4.25v 4 vs = 4.25v 5 vr = 4.50v 5 vs = 4.50v 6 vr = 4.75v 6 vs = 4.75v 7 vr = 5.00v 7 vs = 5.00v restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status vr [2:0] vs [2:0] power on sequence 3h 5h s/w reset 3h 5h h/w reset 3h 5h flow chart legend command parameter display action mode sequential transfer regctr 1 st paramete r www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 146 confidential leadis technology 7.1.45 vcomctr: vcoml / vcomh voltage control (c1h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) vcomctr 0 1 - 1 1 0 0 0 0 0 1 (c1h) 1 st parameter 1 1 - - - vclc5 vclc4 vclc3 vclc2 vclc1 vclc0 - 2 nd parameter 1 1 - - - vchc5 vchc4 vchc3 vchc2 vchc1 vchc0 - note: ?-? don?t care description vcoml / vcomh voltage control the 1 st parameter: vcoml voltage control (see below table) the 2 nd parameter: vcomh voltage control (see below table) vclc [5:0] vcoml output voltage vchc [5:0] vcomh output voltage 0 vcoml = -2.00 v 0 vcomh = +2.50 v 1 vcoml = -1.95 v 1 vcomh = +2.55 v 2 vcoml = -1.90 v 2 vcomh = +2.60 v : : : : 60 vcoml = +1.00v 60 vcomh = +5.50v 61 ~ 63 not permitted 61 ~ 63 not permitted restriction default value of vcomh will be fixed to the trimmed value during wafer test. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status vclc [5:0] vchc [5:0] power on sequence 32h see note s/w reset 32h see note h/w reset 32h see note note: after wafer level test, the default value of vchc will be trimmed to fit the target vcom amplitude . flow chart legend command parameter display action mode sequential transfer vcomctr 1 st parameter: vclc [5:0] 2 nd parameter: vchc [5:0] www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 147 confidential leadis technology 7.1.46 gamctr1: set gamma correction characteristics (c8h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gamctr1 0 1 - 1 1 0 0 1 0 0 0 (c8h) 1 st parameter 1 1 - gs102 gs101 gs100 gs112 gs111 gs110 2 nd parameter 1 1 - gs122 gs121 gs120 gs132 gs131 gs130 3 rd parameter 1 1 - gs142 gs141 gs140 gs152 gs151 gs150 4 th parameter 1 1 - gs162 gs161 gs160 gs172 gs171 gs170 description set the gray scale voltage to adjust the gamma characteristics of the tft panel. it apply to gamma curve selectio n by instruction code 26h. 1 st to 4 th parameter: gamma curve1 adjustment register restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status gs10[2:0] ~ gs17[2:0] power on sequence 4/4/4/4/4/4/4/4 s/w reset 4/4/4/4/4/4/4/4 h/w reset 4/4/4/4/4/4/4/4 flow chart gamctr1 1 st paramete r 2 nd parameter ????.. 4 th parameter legend command parameter display action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 148 confidential leadis technology 7.1.47 gamctr2: set gamma correction characteristics (c9h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gamctr2 0 1 - 1 1 0 0 1 0 0 1 (c9h) 1 st parameter 1 1 - gs202 gs201 gs200 gs212 gs211 gs210 2 nd parameter 1 1 - gs222 gs221 gs220 gs232 gs231 gs230 3 rd parameter 1 1 - gs242 gs241 gs240 gs252 gs251 gs250 4 th parameter 1 1 - gs262 gs261 gs260 gs272 gs271 gs270 description set the gray scale voltage to adjust the gamma characteristics of the tft panel. it apply to gamma curve selectio n by instruction code 26h. 1 st to 4 th parameter: gamma curve2 adjustment register restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status gs20[2:0] ~ gs27[2:0] power on sequence 4/4/4/4/4/4/4/4 s/w reset 4/4/4/4/4/4/4/4 h/w reset 4/4/4/4/4/4/4/4 flow chart gamctr2 1 st paramete r 2 nd parameter ????.. 4 th parameter legend command parameter display action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 149 confidential leadis technology 7.1.48 gamctr3: set gamma correction characteristics (cah) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gamctr3 0 1 - 1 1 0 0 1 0 1 0 (cah) 1 st parameter 1 1 - gs302 gs301 gs300 gs312 gs311 gs310 2 nd parameter 1 1 - gs322 gs321 gs320 gs332 gs331 gs330 3 rd parameter 1 1 - gs342 gs341 gs340 gs352 gs351 gs350 4 th parameter 1 1 - gs362 gs361 gs360 gs372 gs371 gs370 description set the gray scale voltage to adjust the gamma characteristics of the tft panel. it apply to gamma curve selectio n by instruction code 26h. 1 st to 4 th parameter: gamma curve3 adjustment register restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status gs30[2:0] ~ gs37[2:0] power on sequence 4/4/4/4/4/4/4/4 s/w reset 4/4/4/4/4/4/4/4 h/w reset 4/4/4/4/4/4/4/4 flow chart gamctr3 1 st paramete r 2 nd parameter ????.. 4 th parameter legend command parameter display action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 150 confidential leadis technology 7.1.49 gamctr4: set gamma correction characteristics (cbh) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) gamctr4 0 1 - 1 1 0 0 1 0 1 1 (cbh) 1 st parameter 1 1 - gs402 gs401 gs400 gs412 gs411 gs410 2 nd parameter 1 1 - gs422 gs421 gs420 gs432 gs431 gs430 3 rd parameter 1 1 - gs442 gs441 gs440 gs452 gs451 gs450 4 th parameter 1 1 - gs462 gs461 gs460 gs472 gs471 gs470 description set the gray scale voltage to adjust the gamma characteristics of the tft panel. it apply to gamma curve selectio n by instruction code 26h. 1 st to 4 th parameter: gamma curve4 adjustment register restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status gs40[2:0] ~ gs47[2:0] power on sequence 4/4/4/4/4/4/4/4 s/w reset 4/4/4/4/4/4/4/4 h/w reset 4/4/4/4/4/4/4/4 flow chart gamctr4 1 st paramete r 2 nd parameter ????.. 4 th parameter legend command parameter display action mode sequential transfer www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 151 confidential leadis technology 7.1.50 eppgmdb: write id2, vcom offset value inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) eppgmdb 0 1 - 1 1 0 1 0 0 0 0 (d0h) parameter 1 1 - - - - - - vcof82 vcof81 vcof80 - parameter 1 1 - - - vcof5 vcof4 vcof3 vcof2 vcof1 vcof0 - parameter 1 1 - id26 id25 id24 id23 id22 id21 id20 db_sel - note: ?-? don?t care description this command is used to write the values of id2 , vcom and vcom8 to internal register. these value is programmed into eeprom by command ?eppgm(d2h). vcom offset control 1 st parameter: vcom offset control(8color) vcof8 [2:0] vclc (internal) vchc (internal) 0(default) vclc vchc 1 vclc-3 vchc-3 2 vclc-2 vchc-2 3 vclc-1 vchc-1 4 vclc vchc 5 vclc+1 vchc+1 6 vclc+2 vchc+1 7 vclc+3 vchc+3 2 nd parameter: vcom offset control vcof [5:0] vclc (internal) vchc (internal) 0(default) vclc vchc 1 vclc-31 vchc-31 : : : 31 vclc-1 vchc-1 32 vclc vchc 33 vclc+1 vchc+1 : : : 63 vclc+31 vchc+31 note: if vclc (internal) or vchc (internal) is less than 0, it becomes 0. if vclc (internal) or vchc (internal) is larger than 31, it becomes 31. the vcof[5:0] is stored in eeprom to fit contrast. 3 rd parameter: id2[6:0] write 7-bit lcd module/driver version id to save it to eeprom. 3 rd parameter: db_sel ?0? = using the eeprom data for making vcomh & vcoml. ?1? = using the internal register values written by eppgmdb for vcomh & vcoml. the following drawing shows how to use ?db_sel? to fix the vcof and the vcof8. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 152 confidential leadis technology the user shoule fix vcof and vcof8 to adjust the vcomh and vcoml output voltage level. the user can use ?db_sel? to find out which value is suitable for vcomh and vcoml. if the user sets ?db_sel? to ?1?, then LDS285 uses the internal register value to make the proper vcomh and vcoml output voltage instead of the value read from eeprom. that means that the user can control and monitor the vcomh and vcoml output voltage by changing the parameter of the command ?eppgmdb? and find out the proper value of the 1 st and the 2 nd parameter of the command ?eepgmdb? before programming the vcof[5:0] and vcof8[2:0] into eeprom. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes eeprom vcof[5:0] vcof8[2:0 vcom gen mpu by command eppgmdb internal register m u x vcof[5:0] vcof8[2:0] LDS285 db_sel : ?0? : eeprom data is used ?1? : internal register data is used vcoml vcomh www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 153 confidential leadis technology default default value status vcof8[2:0] vcof[5:0] id2 db_sel power on sequence 0 0 not fixed (80 ~ ffh) 0 s/w reset 0 0 not fixed (80 ~ ffh) 0 h/w reset 0 0 not fixed (80 ~ ffh) 0 flow chart legend command parameter dis p la y action mode sequential transfer eppgmdb (d0h) send 1 st p arameter send 2 nd p arameter send 3 rd p arameter www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 154 confidential leadis technology 7.1.51 eperase: eprom erase (d1h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) eperase 0 1 - 1 1 0 1 0 0 0 1 (d1h) parameter no parameter description eeprom data erase. restriction it will be necessary to wait more than 150msec after eeprom erase start . refer to 7.3.3&7.3.4 eeprom access flow. eperase should be excuted in sleep-in mode. register availability status availability normal mode on, idle mode off, sleep out no normal mode on, idle mode on, sleep out no partial mode on, idle mode off, sleep out no partial mode on, idle mode on, sleep out no sleep in yes default status default value power on sequence disable s/w reset disable h/w reset disable flow chart legend command display action mode sequential transfer eperase www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 155 confidential leadis technology 7.1.52 epprog: eprom program (d2h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) epprog 0 1 - 1 1 0 1 0 0 1 0 (d2h) parameter no parameter description eeprom data program. restriction it will be necessary to wait more than 100msec after eeprom program start . refer to 6.3.3&6.3.4 eeprom access flow. eeprog should be excuted in sleep-in mode. register availability status availability normal mode on, idle mode off, sleep out no normal mode on, idle mode on, sleep out no partial mode on, idle mode off, sleep out no partial mode on, idle mode on, sleep out no sleep in yes default status default value power on sequence disable s/w reset disable h/w reset disable flow chart legend command display action mode sequential transfer epprog www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 156 confidential leadis technology 7.1.53 eprdvrf: eprom read verify (d3h) inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) eprdvrf 0 1 - 1 1 0 1 0 0 1 1 (d3h) parameter 1 1 - - - - - r e a d pgm vf ervf 0 description .when read =1, pgmvf =0 & ervf =0 , then eeprom data are normally read to internal register. .when read =0, pgmvf =1 & ervf =0, then the read verification for the programmed data will be executed by using the internal reference voltage(vdd1). this mode is to read the programmed value from eeprom under the more serious condition than normal read mode. .when read =0, pgmvf =0 & ervf = 1, then the read verification for the erased data verification will be executed by using the external reference voltage.(me_cmp ). this mode is to read the erased value from eeprom under the more serious condition than normal read mode. restriction it will be necessary to wait more than 100usec after eeprom read start . refer to 7.3.3&6.3.4 eeprom access flow. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence disable s/w reset disable h/w reset disable flow chart legend command display action mode sequential transfer epread www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 157 confidential leadis technology 7.1.54 rdvcof: vcom offset registers bits read back (d9h) inst / para dc wr b rd b d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) rdvcof 0 1 - 1 1 0 1 1 0 0 1 (d9h) dummy read 1 1 - - - - - - - - - dummy 2?nd parameter 1 1 - - - rvcof5 rvcof4 rvcof3 rvcof2 rvcof1 rvcof0 3?rd parameter 1 1 - - - - - - rvcof82 rvcof81 rvcof80 description this read 6-bit vcom register offset value and additional 4-bit vcom offset value. ( refer to 6.1.60 ) the 1 st parameter is dummy data the 2 nd parameter rvcof[5:0] : range 0d ~ 63d the 2 nd parameter rvcof8[2:0]: range 0 ~ 7. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status rvcof[5:0], rvcof8[2:0] power on sequence - s/w reset - h/w reset - flow chart legend command parameter dis p la y action mode sequential transfer serial i/f mode rdvcof send 2 nd p arameter rdvcof dumm y read send 2 nd p arameter host driver parallel i/f mode send 3 rd p arameter send 3 rd p arameter www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 158 confidential leadis technology 7.1.55 ledctrl: write the conf iguration for led driver inst / para dc wrb rdb d17-8 d7 d6 d5 d4 d3 d2 d1 d0 (code) eppgmdb 0 1 - 1 1 1 0 1 1 1 1 (efh) parameter 1 1 - - - - - - - - type - parameter 1 1 - 0 adr2 adr1 adr0 db3 db2 db1 db0 - parameter 1 1 - 0 per3 per2 per1 per0 0 0 0 - note: ?-? don?t care description this command is used to configure the led driver control 1 st parameter: type ?0? : when LDS285 controls led driver type with pwm pulse contol. ?1? : when LDS285 controls led driver lds8816 with 1-wire digital interface. 2 nd parameter: adr[2:0], db[3:0] when type = 1, LDS285 write db[3:0] to addr[2:0] register in lds8861. ( please refer to section 6.4 and the specification for lds8861 ) 3 rd parameter: per[3:0] when type = 0, per[3:0] decide the period of pwm pulse which is sent through lcd_cnt. (please refer to section 6.4 ) restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status type adr[2:0] db[3:0] per[3:0] power on sequence 0 0 eh 0 s/w reset 0 0 eh 0 h/w reset 0 0 eh 0 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 159 confidential leadis technology flow chart legend command parameter dis p la y action mode sequential transfer ledctrl(efh) send 1 st p arameter send 2 nd p arameter send 3 rd p arameter www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 160 confidential leadis technology 7.2 reset table (default value) (tbd) item after power on after hardware reset after software reset ddram random no change no change sleep in/out in in in display on/off off off off display mode (normal/partial) normal normal normal display inversion on/off off off off display idle mode on/off off off off column: start address (xs) 0000h 0000h 0000h column: end address (xe) 00efh 00efh 007fh (239d) (when mv=0) 009fh (319d) (when mv=1) row: start address (ys) 0000h 0000h 0000h row: end address (ye) 013fh 013ffh 009fh (319d) (when mv=0) 007fh (239d) (when mv=1) brightness control value *3) ffh ffh ffh gamma setting gc0 gc0 gc0 partial: start address (psl) 0000h 0000h 0000h partial: end address (pel) 013fh 013fh 013fh tearing: on/off off off off tearing effect mode *4) 0 (mode1) 0 (mode1) 0 (mode1) memory data access control (my/mx/mv/ml/rgb) 0/0/0/0/0 0/0/0/0/0 no change interface pixel color format 7 (24-bit/pixel) 7 (24-bit/pixel) no change rddpm 08h 08h 08h rddmadctr 00h 00h no change rddcolmod 7 (24-bit/pixel) 7 (24-bit/pixel) no change rddim 00h 00h 00h rddsm 00h 00h 00h rddsdr 00h 00h 00h id1 tbd tbd tbd id2 tbd tbd tbd id3 tbd tbd tbd notes: 1. there will be no abnormal visible effects on the display when s/w or h/w reset is applied. 2. powered-on reset finishes within 10s after both vdd1_io, vdd1 & vdd2 are applied. 3. brightness conrol value is related with the command ?wrdisbv(51h). 4. te mode 1 means tearing effect output line consists of v-blanking information only. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 161 confidential leadis technology 7.3 instruction setup flow 7.3.1 initializing with the built-in power supply circuits (tbd) h/w reset ? power input: vss, vdd1 and vdd2 (any order) wait until power stabilization ? !res = ?l? wait for more than 10 s ? !res = ?h? wait for more than 5ms power supply set ? slpout (sleep mode off & osc/booster on) initializing start (power on) initializing end display environment set2 (if not used, can be skipped) ? invon / invoff (display inversion / normal set) ? idmon / idmoff (idle mode on/off) ? ptlar / ptlon / ptloff (partial area set & partial on/off) - partial start/end line set (psb, peb) ? scrlar (area scroll set) - top fixed area, scroll area and bottom fixed area set (tfa, vsa, bfa) ? vscsad (scroll start address set) - scroll start address (ssa) ? madctr (memory data access control) - row direction (my), column direction (mx), address direction (v), scan direction (ml) and rgb order ? colmod (interface pixel format set) ? wrctrld ( brightness control) on/off display data write & display on ? raset / caset (row/column address set) - start/end row address set (ys, ye), start/end column address set (xs, xe) ? ramwr (memory data write) wait for more than 120ms after power control command ? dispon (display on) fig. 7.3.1 initializing with the built-in power supply circuits the initializing sequence does not have any effect on the display. the display is in its normal background color during the initialization. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 162 confidential leadis technology 7.3.2 power off sequence (tbd) ? dispoff (display off) all of the common & segment pins become vc potential. power off start (without h/w reset) power off end ? slpin (sleep in) all the liquid crystal power supply circuits and oscillator circuit become off. stop the power supply: vdd2 and vdd1 stop (any order) h/w reset ? !res = ?l? wait for more than 10 s ? !res = ?h? power off start (with h/w reset) power off end stop the power supply: vdd2 and vdd1 stop (any order) fig. 7.3.2 power off sequence www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 163 confidential leadis technology 7.3.3 eeprom access sequence fo r initialization (data clear) * slpout command end extc = vdd1 reset start * erase verify command : eprdvrf ( d3h ) 1 st parameter : 02h apply 21.0v ~ 23.0v at me_cmp pad * eperase command wait for more than 150msec remove me_cmp external power * rdvcof command * rddid2 command read data all ?0?? yes no eeprom data clear eeprom clear data verification www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 164 confidential leadis technology 7.3.4 eeprom access sequence for program (data write) (tbd) apply 8.2v ~ 8.8v at me_cmp pad * epprog command wait for more than 40msec remove me_cmp external power extc = vdd1 reset start eeprom programming * epprom data write to internal register command : eppgmdb (d0h) 1 st parameter : {5?b0,vcof8[2:0]} 2 nd parameter: {2?b0, vcof[5:0]} 3 rd parameter: {id2[6:0],db_sel} * slpout command end read data all correct? yes no eeprom programming verify re-execute eeprom initialization (clear) refer to 7.3.3 * program verify command : eprdvrf ( d3h ) 1 st parameter : 04h * rdvcof command * rddid2 command www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 165 confidential leadis technology 8 specifications 8.1 absolute maximum ratings (v ss = 0v) item symbol value unit supply voltage (1) v dd1 - 0.3 ~ + 2.0 v supply voltage (2) v dd2 - 0.3 ~ + 3.6 v drive supply voltage vgh ? vgl - 0.3 ~ + 28.0 v logic input voltage range v in - 0.3 ~ v dd1 + 0.3 v logic output voltage range v o - 0.3 ~ v dd1 + 0.3 v operating temperature range t opr - 30 ~ + 75 c storage temperature range t stg - 55 ~ + 125 c note: if the absolute maximum rating of even is one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings 8.2 esd protection level table 8.2.1 esd models. model test condition protection level unit human body model c = 100 pf, r = 1.5 k > 2000 v machine model c = 200 pf, r = 0.0 > 200 v 8.3 latch-up protection level the device will not latch up at trigger current levels less than 100 ma. 8.4 light sensitivity the operation of the ic will not be materially altered by incident light. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 166 confidential leadis technology 8.5 maximum series resistance the driver will operate in ?chip on glass? applications with series resistances (due to ito track resistance). voltages are specified at module i/o assuming maximum values as in table 7.5.1. table 8.5.1 maximum series resistance on module. name type maximum series resistance unit vdd1 power supply 10 vdd2 power supply 10 vss power supply 10 osc input 100 srgb, sinv, smx, smy, vglx4, frm, extc, psel tgs, test2, test3 input 100 p68, bs2, bs1, bs0 input 100 resb input 100 csb (!sce) input 100 dc (scl) input 100 wrb input 100 rdb input 100 te, vsynco output 100 d15 to d0 input / output 100 d23 to d16, vdo dck, enable, vsync, hsync input 100 vgh capacitor connection 10 vgl capacitor connection 10 vcomh,vcoml capacitor connection 10 vr capacitor connection 10 vs capacitor connection 10 vreg_dc capacitor connection 5 vdc1 booster1 power supply 5 c1p, c1m capacitor connection 10 c2p, c2m capacitor connection 10 c3p, c3m capacitor connection 10 c4p, c4m capacitor connection 10 c5p, c5m capacitor connection 10 c6p, c6m capacitor connection 10 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 167 confidential leadis technology 8.6 dc characteristics 8.6.1 basic characteristics (v ss =0v, v dd1 =1.65v to 1.95v, v dd2 =2.3v to 2.9v,ta = -30 to 70 c) parameter symbol conditions related pins min typ max unit power & operating voltages i/o interface voltage v dd1io - *2) vdd1_io,vdd1 1.65 1.8/2.75 3.3 logic operating voltage v dd1 psel=0 *2) vdd1 1.65 1.8 1.95 analog operating voltage v dd2 - *2) vdd2 2.3 2.75 3.3 gate drive high voltage1 vgh *3) vgh 9 16.0 20.0 gate drive low voltage1 vgl *3) vgl -15 -12.0 -6.0 drive supply voltage1 vgh-vgl *3) vgh, vgl 15 28.0 30 v input / output high level input voltage v ih *1) *2) 0.7v dd1 - v dd1 low level input voltage v il - *1) *2) v ss - 0.3v dd1 high level output voltage v oh i oh = -1.0ma 0.8v dd1 - v dd1 low level output voltage v ol i ol = +1.0ma *2) d17 to d0, te, test1 v ss - 0.2v dd1 v input leakage current i il v in = v dd1 or v ss *1) *2) -1.0 - +1.0 a oscillator frequency f osc - - 450 500 550 khz booster avdd boost voltage1 avdd1 iavdd=1ma, dual-type, x2 *3) avdd 1.9*vdd2 - 2.0*vdd2 avdd boost voltage2 avdd2 iavdd=1ma, single-type, x2 *3) avdd 1.8*vdd2 - 2.0*vdd avdd boost voltage3 avdd3 iavdd=1ma, single-type, x3 *3) avdd 2.7*vreg _ dc 3.0*vreg _ dc vgh boost voltage vgh i gh =300ua, 4*vr *3) vgh 3.6*vr - 4.0*vr vgl boost voltage vgl i gl =-300ua, -3*vr *3) vgl -2*vr - -1.8*vr vcl boost voltage vcl i cl =-300ua, -1*v dd2 *3) vcl -1*vdd2 - -0.9*vdd2 vs output voltage vs default, no load *3) vs 3.00 4.2 6.00 vr output voltage vr default, no load *3) vr 3.00 4.00 5.00 v note: *1) srgb, sinv, smx, smy, dck, enable, vs ync, hsync, osc, p68, ,bs2, bs1, bs0, csb, resb, dc, wrb, rdb, d23 to d0 pins *2) *3) when the measurement are performed with lcd module, measurement points are like below measurement point for *3) measurement point for *2) capacitor connector pin or flex side fpc lcd panel www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 168 confidential leadis technology parameter symbol conditions related pins min typ max unit vcom generator vcom amplitude vcoma no load vcomh vcoml v vcom output high resistance r vcomh vcom output = high i vcom = 1ma vcom - 200 tbd vcom output low resistance r vcoml vcom output = low i vcom = 1ma vcom - 200 tbd source driver gray scale resistance rgray rap~rjp, ran~rjn, r0~r62 of gray voltage generator s1 to s720 0.7*rx rx 1.3*rx i vosh vs=3.75v, vso=v0 at positive, vout=v0-2v s1 to s720 - -200 -100 a *1) *2) drive output current i vosl vs=3.75v, vso=v0 at negative, vout=v0-2v s1 to s720 100 200 - a vss1+1.0 ~ vs-1.0 s1 to s720 - 10 20 mv output voltage deviation d vos vss1+0.1v ~ vss1+1.0 vs-1.0 ~ vs-0.1v s1 to s720 - 30 50 mv output voltage range v os - s1 to s720 0.1 - vs-0.1 v gate driver *3) output on resistance r ong ta = 25 c g1 to g320 - 2 3 k note: 1) v so is the output voltage of source output pins s1 to s720. 2) v out is the applied voltage to source output pins s1 to s720 3) resistance value when -0.1[ma] is applied during the on status of the gate output pin g1 to g320. r on [ ? ] = v [v] / 0.1[ma] ( v: voltage change when ?0.1[ma] is applied in the on status.) www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 169 confidential leadis technology 8.6.2 current consumption current consumption typical worst case host i/f mode of operation frame frequency inversion mode image memory data access control (my:mx:mv) vdd2 (ma) vdd1 (ma) vdd2 (ma) vdd1 (ma) tbd note 1 x;x;x tbd tbd tbd tbd tbd note 2 x;x;x tbd tbd tbd tbd tbd note 3 x;x;x tbd tbd tbd tbd tbd note 4 x;x;x tbd tbd tbd tbd - normal mode on - partial mode off - idle mode off - sleep out mode 60hz tbd note 5 x;x;x tbd tbd tbd tbd - normal mode on - partial mode off - idle mode on - sleep out mode 60hz tbd note 5 x;x;x tbd tbd tbd tbd - normal mode off - partial mode on (32 lines) - idle mode off - sleep out mode 60hz tbd grey levels x;x;x tbd tbd tbd tbd tbd note 6 x;x;x tbd tbd tbd tbd - normal mode off - partial mode on (32 lines) - idle mode on - sleep out mode 60hz tbd note 7 x;x;x tbd tbd tbd tbd host interface not active - sleep in mode n/a n/a n/a x;x;x 0.002 0.010 0;0;0 tbd tbd tbd tbd 0;0;1 tbd tbd tbd tbd 0;1;0 tbd tbd tbd tbd 0;1;1 tbd tbd tbd tbd 1;0;0 tbd tbd tbd tbd 1;0;1 tbd tbd tbd tbd 1;1;0 tbd tbd tbd tbd 262k colors note 8 cpu access @ 15fps 1;1;1 tbd tbd tbd tbd 0;0;0 tbd tbd tbd tbd 0;0;1 tbd tbd tbd tbd 0;1;0 tbd tbd tbd tbd 0;1;1 tbd tbd tbd tbd 1;0;0 tbd tbd tbd tbd 1;0;1 tbd tbd tbd tbd 1;1;0 tbd tbd tbd tbd host interface active - normal mode on - partial mode off - idle mode off - sleep out mode 60hz tbd 262k colors note 8 cpu access @ 25fps 1;1;1 tbd tbd tbd tbd note: x do not care 1. all pixels black 2. checker board one by one 3. checker board 4 by 4 4. grey-scale from top to bottom 5. 20% black, 80%white 6. black & white checker board 8 by 8. 7. absolute worst case patterns: defined by display supplier 8. absolute worst case patterns and sequences: defined by display supplier 9. absolute worst case vdd current is less than tbd ma in the case of cpu access is inactive, normal mode on, partial mode off, idle mode off, sleep out mode. 10. absolute worst case vdd1_ioi current is less than tbd ma in the case of cpu access is inactive, normal mode on, partial mode off, idle mode off, sleep out mode. 11. inrush currents are not included in current consumption values typical case: t a = 25oc vdd2 = 2.75v vdd1 = 1.8v worst case: t a = -30 to70oc vdd2 = 2.5v to 2.9v vdd1 = 1.65v to 1.95v includes process variance. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 170 confidential leadis technology 8.7 ac characteristics(tbd) 8.7.1 parallel interface characteristics (8080-series mpu) !wr !rd d17 to d0 v ih v il t ast t wrl d/!c v ih v il t aht v ih v il t dst t dht v ih v il t rat/ t ratfm t odh t wrh t wc t rdl/ t rdlfm t rdh/ t rdhfm v oh v ol v oh v ol !cs v ih v il t cs t csf t rcs/ t rcsfm v ih v il t csf t chw t chw t aht t rc/ t rcfm t csh fig. 8.7.1 parallel interface characteristics (8080-series mpu) (v ss =0v, v dd1 =1.65v to 1.95v, v dd2 =2.5v to 2.9v,ta = -30 to 75 c signal symbol parameter min max unit description dc t ast t aht address setup time address hold time (write/read) 10 10 - - ns - csb t chw t cs t rcs t rcsfm t csf t csh chip select ?h? pulse width chip select setup time (write) chip select setup time (read id) chip select setup time (read fm) chip select wait time (write/read) chip select hold time 0 35 45 355 10 10 - - - - - - ns - wrb t wc t wrh t wrl write cycle control pulse ?h? duration control pulse ?l? duration 100 35 35 - - - ns - rdb (id) t rc t rdh t rdl read cycle (id) control pulse ?h? duration (id) control pulse ?l? duration (id) 160 90 45 - - - ns when read id data rdb (fm) t rcfm t rdhfm t rdlfm read cycle (fm) control pulse ?h? duration (fm) control pulse ?l? duration (fm) 450 90 355 - - - ns when read from ddram d17 to d0 t dst t dht t rat t ratfm t odh data setup time data hold time read access time (id) read access time (fm) output disable time 10 10 - - 20 - - 40 340 80 ns for maximum c l =30pf for minimum c l =8pf note: the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. logic high and low levels are specified as 30% and 70% of vdd1 for input signals. for output, see section www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 171 confidential leadis technology 7.7.6.1 input signal slope output signal slope v ih =0.7*vdd1 v il =0.3*vdd1 tr tf v oh =0.8*vdd1 v ol =0.2*vdd1 tr tf !wr, !rd t csf t wc !cs t chw min. 5ns n ote: logic high and low levels are specified as 30% and 70% of vdd1io for fig. 8.7.2 chip select timing !wr !rd twrh !cs trdh trdhfm n ote: logic high and low levels are spec ified as 30% and 70 % of vdd1io for input fig. 8.7.3 write to read and read to write timing www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 172 confidential leadis technology 8.7.2 parallel interface characteristics (6800-series mpu) d/!c r/!w e d1 to d0 v ih v il v ih v il t ast t aht v ih v il t dst t dht v ih v il t rat/ t ratfm t odh t wrh v ih v il t wrl t wc !cs v ih v il t cs t csf t rc/ t rcfm t rdh/ t rdhfm t rdl/ t rdlfm t chw t chw t aht t rcs/ t rcsfm t csh fig. 8.7.4 parallel interface characteristics (6800-series mpu) (v ss =0v, v dd1 =1.65v to 1.95v, v dd2 =2.5v to 2.9v,ta = -30 to 75 c) signal symbol parameter min max unit description dc t ast t aht address setup time address hold time (write/read) 10 10 - - ns csb t chw t cs t rcs t rcsfm t csf t csh chip select ?h? pulse width chip select setup time (write) chip select setup time (read id) chip select setup time (read fm) chip select wait time (write/read) chip select hold time 0 35 45 355 10 10 - - - - - - ns - wrb t wc t wrh t wrl write cycle control pulse ?h? duration control pulse ?l? duration 100 35 35 - - - ns rdb (id) t rc t rdh t rdl read cycle (id) control pulse ?h? duration (id) control pulse ?l? duration (id) 160 90 45 - - - ns when read id data rdb (fm) t rcfm t rdhfm t rdlfm read cycle (fm) control pulse ?h? duration (fm) control pulse ?l? duration (fm) 450 90 355 - - - ns when read from ddram d17 to d0 t dst t dht t rat t ratfm t odh data setup time data hold time read access time (id) read access time (fm) output disable time 10 10 - - 20 - - 40 340 80 ns for maximum c l =30pf for minimum c l =8pf note: the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. logic high and low levels are specified as 30% and 70% of vdd1_io for input signals. for output, see section 7.7.6.1 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 173 confidential leadis technology input signal slope output signal slope v ih =0.7*vdd1 v il =0.3*vdd1 tr tf v oh =0.8*vdd1 v ol =0.2*vdd1 tr tf www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 174 confidential leadis technology 8.7.3 serial interface characte ristics (3-pin serial) v ih v il t shw/ t shr t slw/ t slr t css !sce scl t csh t scycw/ t scycr t sds t sdh sda (sdo) t acc t oh t scc t chw t f t r sda (sdi) fig. 8.7.5 3-pin serial interface characteristics (v ss =0v, v dd1 =1.65v to 1.95v, v dd2 =2.5v to 2.9v,ta = -30 to 75 c) parameter symbol conditions min typ max unit serial clock cycle (write) scl ?h? pulse width (write) scl ?l? pulse width (write) t scycw t shw t slw scl 100 35 35 - - ns data setup time (write) data hold time (write) t sds t sdh sda 30 30 - - ns serial clock cycle (read) scl ?h? pulse width (read) scl ?l? pulse width (read) t scycr t shr t slr scl 150 60 60 - - - ns access rime t acc sda for maximum c l =30pf for minimum c l =8pf 10 50 ns output disable time t oh sda for maximum c l =30pf for minimum c l =8pf 15 50 ns scl to chip select t scc !sce 15 ns sceb ?h? pulse width t chw !sce 45 ns chip select setup time chip select hold time t css t csh !sce 60 65 - - ns note: the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. logic high and low levels are specified as 30% and 70% of vdd1 for input signals. for output, see section 7.7.6.2 input signal slope output signal slope v ih =0.7*vdd1 v il =0.3*vdd1 tr tf v oh =0.8*vdd1 v ol =0.2*vdd1 tr tf www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 175 confidential leadis technology 8.7.4 serial interface characteristics (4-pin serial) v ih v il t shw/ t shr t slw/ t slr t css !sce scl t csh t scycw/ t scycr t sds t sdh sda (sdo) t acc t oh t scc t chw t f t r t dcs t dch sda (sdi) d/!c fig. 8.7.6 4-pin serial interface characteristics (v ss =0v, v dd1 =1.65v to 1.95v, v dd2 =2.5v to 2.9v,ta = -30 to 75 c) parameter symbol conditions min typ max unit serial clock cycle (write) scl ?h? pulse width (write) scl ?l? pulse width (write) t scycw t shw t slw scl 100 35 35 - - ns data setup time (write) data hold time (write) t sds t sdh sda 30 30 - - ns dc setup time dc hold time t dcs t dch dc 30 30 - - ns serial clock cycle (read) scl ?h? pulse width (read) scl ?l? pulse width (read) t scycr t shr t slr scl 150 60 60 - - - ns access rime t acc sda for maximum c l =30pf for minimum c l =8pf 10 50 ns output disable time t oh sda for maximum c l =30pf for minimum c l =8pf 15 50 ns scl to chip select t scc !sce 15 ns sceb ?h? pulse width t chw !sce 45 ns chip select setup time chip select hold time t css t csh !sce 60 65 - - ns note: the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. logic high and low levels are specified as 30% and 70% of vdd1 for input signals. for output, see section 7.7.6.2 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 176 confidential leadis technology input signal slope output signal slope v ih =0.7*vdd1 v il =0.3*vdd1 tr tf v oh =0.8*vdd1 v ol =0.2*vdd1 tr tf www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 177 confidential leadis technology 8.7.5 rgb interface characteristics vsync hsync enable dck d23-d1, vd0 v ih v il v ih v il t dcss t dcsh t dds t ddh t dcyc t dlw t dhw t dsyn fig. 8.7.7 rgb interface characteristics (v ss =0v, v dd1 =1.65v to 1.95v, v dd2 =2.5v to 2.9v,ta = -30 to 75 c) symbol parameter conditions related pins min typ max unit t dcyc t dlw t chw dck cycle time dck low time dck high time - dck tbd tbd tbd - - - - ns t dds t ddh rgb data setup time rgb data hold time - dck, d23-d1, vd0 20 20 - - - - ns t dcss t dcsh enable setup time enable hold time - enable 150 150 - - ns t dsyn sync setup time - dck, hsync, vsync 20 - - ns note: the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. input signal slope output signal slope v ih =0.7*vdd1 v il =0.3*vdd1 tr tf v oh =0.8*vdd1 v ol =0.2*vdd1 tr tf www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 178 confidential leadis technology 8.7.6 reset input timing internal status !res t resw t rest resetting initial condition (default for h/w reset) shorter than 5 s normal operation fig. 8.7.8 reset input timing (v ss =0v, v dd1 =1.65v to 1.95v, v dd2 =2.5v to 2.9v,ta = -30 to 75 c) symbol parameter related pins min typ max note unit t resw *1) reset low pulse width resb 10 - - - s - - - 5 when reset applied during sleep in mode ms t rest *2) reset complete time - - 120 when reset applied during sleep out mode ms note: 1) spike due to an electrostatic discharge on resb line does not cause irregular system reset according to the table below. resb pulse action shorter than 5 s reset rejected longer than 10 s reset between 5 s and 10 s reset start 2) during the resetting period, the display will be blanked (the display is entering blanking sequence, which maximum time is 120 ms, when reset starts in sleep out ?mode. the display remains the blank state in sleep in ?mode) and then return to default condition for h/w reset. 3) during reset complete time, id2 and vcomof value in otp will be latched to internal register during this period. this loading is done every time when there is h/w reset complete time (trest) within 5ms after a rising edge of resb. 4) spike rejection also applies during a valid reset pulse as shown below: 5) it is necessary to wait 5msec after releasing resb before sending commands. also sleep out command cannot be sent for 120msec. . 10 s www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 179 confidential leadis technology 8.7.7 measurement conditions 8.7.7.1 t ratfm , t odh measurement condition measurement condition set-up connector lcd panel fpc oscilloscope see ? note ? data generator external components for test condition (pull-down and pull-up cases) which are removed after test: resistor: 3kohm 5% capacitor: 8 or 30pf 10% see ?note? connector pin / measurement point note: capacitances and resistances of the oscilloscope?s probe must be included externals components in these measurements minimum value measurement d(n) [n=0..23] (pulled up) !rd t odh d(n) [n=0..23] (pulled down) 0% 100% 70% measurement circuit pulled down d(n) [n=0..23] (pulled down) 8pf 3kohm measurement point on the connector pin external components on the connector pin measurement circuit pulled up d(n) [n=0..23] (pulled up) 8pf measurement point on the connector pin external components on the connector pin 3kohm vdd1 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 180 confidential leadis technology maximum value measurement d(n) [n=0..23] (pulled up) rdb t odh d(n) [n=0..23] (pulled down) 0% 100% 70% measurement circuit pulled down d(n) [n=0..23] (pulled down) 30pf 3kohm measurement point on the connector pin external components on the connector pin measurement circuit pulled up d(n) [n=0..23] (pulled up) 30pf measurement point on the connector pin external components on the connector pin 20% 80% t rat/ t ratfm 3kohm vdd1 30% www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 181 confidential leadis technology 8.7.7.2 t acc , t oh measurement condition measurement condition set-up connector lcd panel fpc oscilloscope see ? note ? data generator external components for test condition (pull-down and pull-up cases) which are removed after test: resistor: 3kohm 5% capacitor: 8 or 30pf 10% see ?note? connector pin / measurement point note: capacitances and resistances of the oscilloscope?s probe must be included externals components in these measurements minimum value measurement sda (pulled up) scl t oh sda (pulled down) 0% 100% 70% measurement circuit pulled down sda (dout) 8pf 3kohm measurement point on the connector pin external components on the connector pin measurement circuit pulled up sda (dout) 8pf measurement point on the connector pin external components on the connector pin 3kohm vdd1 30% t acc 100% 0% www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 182 confidential leadis technology maximum value measurement sda (pulled up) !rd t oh sda (pulled down) 0% 100% 70% measurement circuit pulled down sda (dout) 30pf 3kohm measurement point on the connector pin external components on the connector pin measurement circuit pulled up sda (dout) 30pf measurement point on the connector pin external components on the connector pin 20% 80% t acc 3kohm vdd1 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 183 confidential leadis technology 9 reference applications 9.1 microprocessor interface 9.1.1 interfacing with 3-pin serial mode (p68 = "l", bs2=?l?, bs1 = "l", bs0 = "l") !res !cs scl open open vd23 to vd1 sda vd0 dck, enable vsync, hsync open mpu LDS285 p68 bs2 bs1 bs0 !res !cs d/!c (scl) !rd !w r (d/!c) d23 to d1 d0 (sda) vd0 dck, enable vsync, hsync vsynco v ss1 graphic controller if rgb interface is not used, please c onnect these pins and d23~d1 pins to vss1 fig. 9.1.1 interfacing with 3-pin serial mode 9.1.2 interfacing with 4-pin serial mode (p68 = "h", bs2=?l?, bs1 = "l", bs0 = "l") !res !cs scl open d/!c vd23 to vd1 sda vd0 dck, enable vsync, hsync open mpu LDS285 p68 bs2 bs1 bs0 !res !cs d/!c (scl) !rd !w r (d/!c) d23 to d1 d0 (sda) vd0 dck, enable vsync, hsync vsynco v ss1 graphic controller if rgb interface is not used, please connect these pins and d23~d1 pins to vss1 v dd1 fig. 9.1.2 interfacing with 4-pin serial mode www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 184 confidential leadis technology 9.1.3 interfacing with 8080-series mpu 8-bit bus (p68 = "l", bs2=?l?, bs1 = "l", bs0 = "h") resb csb d/!c !rd !w r vss1 d7 to d0 vss1 vss1 vss1 open 8080-series mpu LDS285 p68 bs2 bs1 bs0 !res !cs d/!c !rd !w r d23 to d8 d7 to d0 vd0 dck, enable vsync, hsync vsynco v ss1 graphic controller in the parallel interface mode, rgb interface cannot be used v dd1 fig. 9.1.3 interfacing with 8-bit 8080-series 9.1.4 interfacing with 6800-series mpu 8-bit bus (p68 = "h", bs2=?l?, bs1 = "l", bs0 = "h") resb csb rs e r/!w vss1 d7 to d0 vss1 vss1 vss1 open 6800-series mpu LDS285 p68 bs2 bs1 bs0 !res !cs d/!c (rs) !rd (e) !w r (r/!w ) d23 to d8 d7 to d0 vd0 dck, enable vsync, hsync vsynco v ss1 graphic controller in the parallel interface mode, rgb interface cannot be used v dd1 fig. 9.1.4 interfacing with 8-bit 6800-series www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 185 confidential leadis technology 9.1.5 interfacing with 8080-series mpu 9-bit bus (p68 = "l", bs2=?h?, bs1 = "l", bs0 = "l") !res !cs d/!c !rd !w r vss1 d8 to d0 vss1 vss1 vss1 open 8080-series mpu LDS285 p68 bs2 bs1 bs0 !res !cs d/!c !rd !w r d23 to d9 d8 to d0 vd0 dck, enable vsync, hsync vsynco v ss1 graphic controller in the parallel interface mode, rgb interface cannot be used v dd1 fig. 9.1.5 interfacing with 8-bit 8080-series 9.1.6 interfacing with 6800-series mpu 9-bit bus (p68 = "h", bs2=?h?, bs1 = "l", bs0 = "l") resb csb rs e r/!w vss1 d8 to d0 vss1 vss1 vss1 open 6800-series mpu LDS285 p68 bs2 bs1 bs0 !res !cs d/!c (rs) !rd (e) !w r (r/!w ) d23 to d9 d8 to d0 vd0 dck, enable vsync, hsync vsynco v ss1 graphic controller in the parallel interface mode, rgb interface cannot be used v dd1 fig. 9.1.6 interfacing with 8-bit 6800-series www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 186 confidential leadis technology 9.1.7 interfacing with 8080-series mpu 16-bit bus (p68 = "l", bs2=?l?, bs1 = "h", bs0 = "h") resb csb d/!c !rd !w r vss1 d15 to d0 vss1 vss1 vss1 open 8080-series mpu LDS285 p68 bs2 bs1 bs0 !res !cs d/!c !rd !w r d23 to d16 d15 to d0 vd0 dck, enable vsync, hsync vsynco v ss1 graphic controller in the parallel interface mode, rgb interface cannot be used v dd1 fig. 9.1.7 interfacing with 16-bit 8080-series 9.1.8 interfacing with 6800-series mpu 16-bit bus (p68 = "h", bs2=?l?, bs1 = "h", bs0 = "h") !res !cs rs e r/!w vss1 d15 to d0 vss1 vss1 vss1 vsynco 6800-series mpu LDS285 p68 bs2 bs1 bs0 !res !cs d/!c (rs) !rd (e) !w r (rw ) d23 to d16 d15 to d0 vd0 dck, enable vsync, hsync vsynco v ss1 graphic controller in the parallel interface mode, rgb interface cannot be used v dd1 fig. 9.1.8 interfacing with 16-bit 6800-series www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 187 confidential leadis technology 9.1.9 interfacing with 8080-series mpu 18-bit bus (p68 = "l", bs2=?h?, bs1 = "h", bs0 = "l") resb csb d/!c !rd !w r vss1 d17 to d0 vss1 dck, enable vsync, hsync open 8080-series mpu LDS285 p68 bs2 bs1 bs0 !res !cs d/!c !rd !w r d23 to d18 d17 to d0 vd0 dck, enable vsync, hsync vsynco v ss1 graphic controller in the parallel interface mode, rgb interface cannot be used v dd1 fig. 9.1.9 interfacing with 18-bit 8080-series 9.1.10 interfacing with 6800-series mpu 18-bit bus (p68 = "h", bs2=?h?, bs1 = "h", bs0 = "l") !res !cs rs e r/!w vss1 d17 to d0 vss1 dck, enable vsync, hsync open 6800-series mpu LDS285 p68 bs2 bs1 bs0 !res !cs d/!c (rs) !rd (e) !w r (r/!w ) d23 to d18 d17 to d0 vd0 dck, enable vsync, hsync vsynco graphic controller in the parallel interface mode, rgb interface cannot be used v dd1io v ss1 fig. 9.1.10 interfacing with 18-bit 6800-series www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 188 confidential leadis technology 9.2 connections with lcd panel 9.2.1 one layer connection for gate output rgb filter order = rgb (from left top of the panel) rgb filter order = bgr (from left top of the panel) case1 case2 g320 r g b g319 g320 b g r g319 : b : smx = 1 : b : smx = 1 :: smy = 1 :: smy = 1 : g : srgb = 1 : g : srgb = 0 ::: : : r : s1 = filter b : r : s1 = filter r g4 g3 s2 = filter g g4 g3 s2 = filter g g2 g1 s3 = filter r g2 g1 s3 = filter b s720 s1 ? s720 s1 ? g2 bumps down g1 ?. g2 bumps down g1 ?. ?. g 320 lds284 g319 ?. g320 lds284 g319 case3 case4 g319 r g b g320 g319 b g r g320 : b : smx = 0 : b : smx = 0 :: smy = 1 :: smy = 1 : g : srgb = 0 : g : srgb = 1 ::: : : r : s1 = filter r : r : s1 = filter b g3 g4 s2 = filter g g3 g4 s2 = filter g g1 g2 s3 = filter b g1 g2 s3 = filter r s1 s720 ? s1 s720 ? ?. g1 bumps up g2 ?. ?. g1 bumps up g2 ?. g319 lds284 g320 g319 lds284 g320 case5 case6 g319 lds284 g320 g319 lds284 g320 ?. g1 b umps d own g2 ?. smx = 0 ?. g1 b umps d own g2 ?. smx = 0 s1 s720 smy = 0 s1 s720 smy = 0 g1 r g b g2 srgb = 0 g1 b g r g2 srgb = 1 g3 b g4 g3 b g4 :: s1 = filter r :: s1 = filter b : g : s2 = filter g : g : s2 = filter g :: s3 = filter b :: s3 = filter r : r : ? : r : ? ::: : g319 g320 g319 g320 case7 case8 g320 lds284 g319 g320 lds284 g319 ?. g2 b umps up g1 ?. smx = 1 ?. g2 b umps up g1 ?. smx = 1 s720 s1 smy = 0 s720 s1 smy = 0 g2 r g b g1 srgb = 1 g2 b g r g1 srgb = 0 g4 b g3 g4 b g3 :: s1 = filter b :: s1 = filter r : g : s2 = filter g : g : s2 = filter g :: s3 = filter r :: s3 = filter b : r : ? : r : ? ::: : g320 g319 g320 g319 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 189 confidential leadis technology 9.2.2 two layer connection for gate output rgb filter order = rgb (from left top of the panel) rgb filter order = bgr (from left top of the panel) case9 case10 g2 r g b g1 g2 b g r g1 : b : smx = 1 : b : smx = 1 :: smy = 0 :: smy = 0 : g : srgb = 1 : g : srgb = 0 :::: : r : s1 = filter b : r : s1 = filter r g318 g317 s2 = filter g g318 g317 s2 = filter g g320 g319 s3 = filter r g320 g319 s3 = filter b s720 s1 ? s720 s1 ? g2 bumps down g1 ?. g2 bumps down g1 ?. ?. g320 lds284 g319 ?. g320 lds284 g319 case11 case12 g1 r g b g2 g1 b g r g2 : b : smx = 0 : b : smx = 0 :: smy = 0 :: smy = 0 : g : srgb = 0 : g : srgb = 1 :::: : r : s1 = filter r : r : s1 = filter b g317 g318 s2 = filter g g317 g318 s2 = filter g g319 g320 s3 = filter b g319 g320 s3 = filter r s1 s720 ? s1 s720 ? ?. g1 bumps up g2 ?. ?. g1 bumps up g2 ?. g319 lds284 g320 g319 lds284 g320 case13 case14 g319 lds284 g320 g319 lds284 g320 ?. g1 b umps d own g2 ?. smx = 0 ?. g1 b umps d own g2 ?. smx = 0 s1 s720 smy = 1 s1 s720 smy = 1 g319 r g b g320 srgb = 0 g319 b g r g320 srgb = 1 g317 b g318 g317 b g318 :: s1 = filter r :: s1 = filter b : g : s2 = filter g : g : s2 = filter g :: s3 = filter b :: s3 = filter r : r : ? : r : ? :::: g1 g2 g1 g2 case15 case16 g320 lds284 g319 g320 lds284 g319 ?. g2 b umps up g1 ?. smx = 1 ?. g2 b umps up g1 ?. smx = 1 s720 s1 smy = 1 s720 s1 smy = 1 g320 r g b g319 srgb = 1 g320 b g r g319 srgb = 0 g318 b g317 g318 b g317 :: s1 = filter b :: s1 = filter r : g : s2 = filter g : g : s2 = filter g :: s3 = filter r :: s3 = filter b : r : ? : r : ? :::: g0 g1 g0 g1 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 190 confidential leadis technology 9.3 example connection with panel (case11) frame memory (1,1) (240,320) lcd ( front side ) ic glass glass ic bumps up lcd ( front side ) bumps down (1,1) 240 x 320 panel viewing area LDS285 bumps up s1 - - -- s720 g319 - - g1 g2 - - - g320 smx = vss smy = vss srgb = vss www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 191 confidential leadis technology 9.4 connection example with external components v dd2 v dd vss c3 vdd1 vdd2 vdc1 vreg_dc vs vr avdd c1p c1m c2p c2m c3p c3m c4p c4m c5p c5m c6p c6m vgh vcl vgl vcomh vcoml c1 c1 = 1.0 f ~ 2.2 f(typical :1.0uf) c2 = 1.0 f ~ 2.2 f(typical :2.2uf) c3 = 0.22 f d1 = schottky diode vf(forward) = 0.3v / 50ma c1 c3 c2 c1 c1 c2 c3 c3 c1 c2 c1 c1 d1 d1 d1 c2 optional www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 192 confidential leadis technology 9.4.1 application circuit example note: 1) to use extended command set like eeprom program, extc should be connected to vdd1 and external voltage should be appled to me_cmp pad, so, extc and me_cmp should have probing point for mass production. www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 193 confidential leadis technology 9.5 external components connection pad name connection typical capacitance value vcomh connect to capacitor (max 6v): vcomh---(+)----| |--- (-)------vss 1.0 uf vcoml connect to capacitor (max 3v): vcoml ---(-)----| |--- (+)-----vss 1.0 uf vgl connect to capacitor (max 12v): vgl ---(-)----| |--- (+)-----vss 1.0 uf vcl connect to capacitor (max 5v): vcl ---(-)----| |--- (+)-----vss 1.0 uf vss1_r connect to vss(gnd) vss1 connect to vss(gnd) vss2 connect to vss(gnd) vss2_dc connect to vss(gnd) vdd1_r connect to vdd1 vdd2_dc connect to vdd2 vgh connect to capacitor (max 16v): vgh ---(+)----| |--- (-)-----vss 1.0 uf c6+, c6- connect to capacitor (max 5v): c6+ ---(+)----| |--- (-)-----c6- 1.0 uf c5+, c5- connect to capacitor (max 7v): c5+ ---(+)----| |--- (-)-----c5- 1.0 uf c4+, c4- connect to capacitor (max 7v): c4+ ---(+)----| |--- (-)-----c4- 1.0 uf c3+, c3- connect to capacitor (max 7v): c3+ ---(+)----| |--- (-)-----c3- 1.0 uf c2+, c2- connect to capacitor (max 5v): c2+ ---(+)----| |--- (-)-----c2- 2.2 uf c1+, c1- connect to capacitor (max 5v): c1+ ---(+)----| |--- (-)-----c1- 2.2 uf vdc1 connect to vdd2( in case of x3 avdd3 mode, connect to vreg_dc) vreg_dc connect to capacitor (max 2.6v): vreg_dc ---(+)----| |--- (-)-----vss 2.2 uf avdd connect to capacitor (max 6v): avdd ---(+)----| |--- (-)-----vss 2.2 uf vr connect to capacitor (max 6v): vr ---(+)----| |--- (-)-----vss 1.0 uf vs connect to capacitor (max 6v): vs ---(+)----| |--- (-)-----vss 1.0 uf vdd1 when ?psel = low? vddi (digital power) when ?psel = high? connect to capacitor (max 5v): vdd1 (r) ---(+)----| |--- (-)-----vss 2.2 uf vgl connect to shottky diode between vss vf = 0.3v / 50ma avdd connect to shottky diode between vdd2 vf = 0.3v / 50ma vs connect to shottky diode between vdd2 vf = 0.3v / 50ma www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 194 confidential leadis technology 10 chip information 10.1 chip overview LDS285 bumps up 1140 input pad dimension 60 24 140 70 330 3220 output pad dimension 20 19 21 25 100 (384-1)*60=22980 g1 g3 g317 g319 dummy s720 s719 s001 s000 dummy g320 g318 g4 g2 330 22000 um 60 220 source pad gate pad vcom pad input pad dummy pad a lign mark gate control pad diagnostic pad non-parttern area bump align 40 30 30 30 40 30 100 100 115 280 535 115 280 535 (1) (4) (5) (8) (299) (306) s718 (307) (312) (471) (475) (1194) (1198) (1357) (1362) 100 3220 14420 100 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 195 confidential leadis technology note: * chip size = 22,000 x 1140 (excluding scribe lane) * chip thickness = 410 12 m * bump height = 15 3 m (chip to chip), less than 2 m (pad to pad in one chip) www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 196 confidential leadis technology 10.2 bump information 10.2.1 source / gate / vcom / gate co ntrol / output side dummy pad format size item symbol source / gate / vcom / gate control / / output side dummy pad pad pitch a 20um bump width b 21 um bump length c 100 um bump to bump gap1 (vertical) d 25 um bump to bump gap2 (horizontal) e 19 um bump area b*c 2100 um 2 chip boundary to bump edge f 8.5 um b c d a e chip boundry f www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 197 confidential leadis technology 10.2.2 input / input si de dummy pad format size item symbol input / input side dummy pad pad pitch a 70 um bump width b 50 um bump length c 80 um bump to bump gap (horizontal) e 20 um bump area b*c 4000 um 2 chip boundary to bump edge f 12.5 um b c f a e chip boundry www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 198 confidential leadis technology 10.3 pad coordinates table 10.3.1 pad center coordinates no name x y no name x y 1 dummy -10885 -517.5 51 dummy -7175 -517.5 2 dummy -10815 -517.5 52 smx -7105 -517.5 3 dummy -10745 -517.5 53 d<7> -7035 -517.5 4 dummy -10465 -517.5 54 d<6> -6965 -517.5 5 pada<0> -10395 -517.5 55 d<5> -6895 -517.5 6 pada<1> -10325 -517.5 56 d<4> -6825 -517.5 7 padb<1> -10255 -517.5 57 d<3> -6755 -517.5 8 me_cmp -10185 -517.5 58 d<2> -6685 -517.5 9 me_cmp -10115 -517.5 59 d<1> -6615 -517.5 10 me_cmp -10045 -517.5 60 d<0> -6545 -517.5 11 me_cmp -9975 -517.5 61 sinv -6475 -517.5 12 me_vme5 -9905 -517.5 62 led_cnt -6405 -517.5 13 me_vme5 -9835 -517.5 63 rdb -6335 -517.5 14 d<23> -9765 -517.5 64 wrb -6265 -517.5 15 d<22> -9695 -517.5 65 dc -6195 -517.5 16 d<21> -9625 -517.5 66 csb -6125 -517.5 17 d<20> -9555 -517.5 67 d_vdd1io -6055 -517.5 18 d<19> -9485 -517.5 68 dummy -5985 -517.5 19 d<18> -9415 -517.5 69 frm -5915 -517.5 20 vsynco -9345 -517.5 70 te -5845 -517.5 21 dummy -9275 -517.5 71 test2 -5775 -517.5 22 osc -9205 -517.5 72 test3 -5705 -517.5 23 tgs -9135 -517.5 73 test1 -5635 -517.5 24 d_vdd1io -9065 -517.5 74 test4 -5565 -517.5 25 d_vss1 -8995 -517.5 75 dummy -5495 -517.5 26 p68 -8925 -517.5 76 dummy -5425 -517.5 27 extc -8855 -517.5 77 dummy -5355 -517.5 28 bs0 -8785 -517.5 78 dummy -5285 -517.5 29 bs1 -8715 -517.5 79 dummy -5215 -517.5 30 bs2 -8645 -517.5 80 psel -5145 -517.5 31 srgb -8575 -517.5 81 dummy -5075 -517.5 32 dummy -8505 -517.5 82 dummy -5005 -517.5 33 dummy -8435 -517.5 83 dummy -4935 -517.5 34 vd0 -8365 -517.5 84 dummy -4865 -517.5 35 rsb -8295 -517.5 85 dummy -4795 -517.5 36 vsync -8225 -517.5 86 vss2 -4725 -517.5 37 hsync -8155 -517.5 87 vss2 -4655 -517.5 38 dck -8085 -517.5 88 vss2 -4585 -517.5 39 enable -8015 -517.5 89 vss2 -4515 -517.5 40 d<17> -7945 -517.5 90 vss2 -4445 -517.5 41 d<16> -7875 -517.5 91 vss2 -4375 -517.5 42 d<15> -7805 -517.5 92 vss2 -4305 -517.5 43 d<14> -7735 -517.5 93 vss2 -4235 -517.5 44 d<13> -7665 -517.5 94 vss2 -4165 -517.5 45 d<12> -7595 -517.5 95 vdd2 -4095 -517.5 46 d<11> -7525 -517.5 96 vdd2 -4025 -517.5 47 d<10> -7455 -517.5 97 vdd2 -3955 -517.5 48 d<9> -7385 -517.5 98 vdd2 -3885 -517.5 49 d<8> -7315 -517.5 99 vdd2 -3815 -517.5 50 smy -7245 -517.5 100 vdd2 -3745 -517.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 199 confidential leadis technology - continued - no name x y no name x y 101 vdd2 -3675 -517.5 151 vdd1 -175 -517.5 102 vdd1_io -3605 -517.5 152 vdd1 -105 -517.5 103 vdd1_io -3535 -517.5 153 vdd1 -35 -517.5 104 vdd1_io -3465 -517.5 154 vdd1 35 -517.5 105 vdd1_io -3395 -517.5 155 vdd1 105 -517.5 106 vdd1_io -3325 -517.5 156 vdd1 175 -517.5 107 vdd1_io -3255 -517.5 157 vdd1 245 -517.5 108 vdd1_io -3185 -517.5 158 vdd1 315 -517.5 109 vs -3115 -517.5 159 vdd1 385 -517.5 110 vs -3045 -517.5 160 vdd1 455 -517.5 111 vs -2975 -517.5 161 vdd1_r 525 -517.5 112 vs -2905 -517.5 162 vdd1_r 595 -517.5 113 vs -2835 -517.5 163 vdd1_r 665 -517.5 114 vs -2765 -517.5 164 vdd1_r 735 -517.5 115 vs -2695 -517.5 165 vss1_r 805 -517.5 116 vs -2625 -517.5 166 vss1_r 875 -517.5 117 vdd1_r -2555 -517.5 167 vss1_r 945 -517.5 118 vdd1_r -2485 -517.5 168 vss1_r 1015 -517.5 119 vdd1_r -2415 -517.5 169 vss1_r 1085 -517.5 120 vdd1_r -2345 -517.5 170 vss1_r 1155 -517.5 121 vdd1_r -2275 -517.5 171 vss1_r 1225 -517.5 122 vdd1_r -2205 -517.5 172 vss1_r 1295 -517.5 123 vdd1_r -2135 -517.5 173 vss1_r 1365 -517.5 124 vdd1_r -2065 -517.5 174 vss1_r 1435 -517.5 125 vdd1_r -1995 -517.5 175 vcom 1505 -517.5 126 vss1_r -1925 -517.5 176 vcom 1575 -517.5 127 vss1_r -1855 -517.5 177 vcom 1645 -517.5 128 vss1_r -1785 -517.5 178 vcom 1715 -517.5 129 vss1_r -1715 -517.5 179 vcom 1785 -517.5 130 vss1_r -1645 -517.5 180 vcom 1855 -517.5 131 vss1_r -1575 -517.5 181 vcomh 1925 -517.5 132 vss1_r -1505 -517.5 182 vcomh 1995 -517.5 133 vss1_r -1435 -517.5 183 vcomh 2065 -517.5 134 vss1_r -1365 -517.5 184 vcomh 2135 -517.5 135 vss1_r -1295 -517.5 185 vcomh 2205 -517.5 136 vss1_r -1225 -517.5 186 vcomh 2275 -517.5 137 vss1_r -1155 -517.5 187 vcoml 2345 -517.5 138 vss1 -1085 -517.5 188 vcoml 2415 -517.5 139 vss1 -1015 -517.5 189 vcoml 2485 -517.5 140 vss1 -945 -517.5 190 vcoml 2555 -517.5 141 vss1 -875 -517.5 191 vcoml 2625 -517.5 142 vss1 -805 -517.5 192 vcoml 2695 -517.5 143 vss1 -735 -517.5 193 vr 2765 -517.5 144 vss1 -665 -517.5 194 vr 2835 -517.5 145 vss1 -595 -517.5 195 vr 2905 -517.5 146 vss1 -525 -517.5 196 vr 2975 -517.5 147 vss1 -455 -517.5 197 vr 3045 -517.5 148 vss1 -385 -517.5 198 vr 3115 -517.5 149 vdd1 -315 -517.5 199 vr 3185 -517.5 150 vdd1 -245 -517.5 200 vr 3255 -517.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 200 confidential leadis technology - continued - no name x y no name x y 201 vcl 3325 -517.5 251 vss2 6825 -517.5 202 vcl 3395 -517.5 252 vgl 6895 -517.5 203 vcl 3465 -517.5 253 vgl 6965 -517.5 204 vgh 3535 -517.5 254 vgl 7035 -517.5 205 vgh 3605 -517.5 255 vgl 7105 -517.5 206 vgh 3675 -517.5 256 vgl 7175 -517.5 207 avdd 3745 -517.5 257 vgl 7245 -517.5 208 avdd 3815 -517.5 258 vgl 7315 -517.5 209 avdd 3885 -517.5 259 vgl 7385 -517.5 210 avdd 3955 -517.5 260 vgl 7455 -517.5 211 avdd 4025 -517.5 261 vgl 7525 -517.5 212 avdd 4095 -517.5 262 vgl 7595 -517.5 213 avdd 4165 -517.5 263 vgl 7665 -517.5 214 vreg_dc 4235 -517.5 264 vss2 7735 -517.5 215 vreg_dc 4305 -517.5 265 vss2 7805 -517.5 216 vreg_dc 4375 -517.5 266 vss2 7875 -517.5 217 vdc1 4445 -517.5 267 vss2_dc 7945 -517.5 218 vdc1 4515 -517.5 268 vss2_dc 8015 -517.5 219 vdc1 4585 -517.5 269 vss2_dc 8085 -517.5 220 vdc1 4655 -517.5 270 vss2_dc 8155 -517.5 221 vdc1 4725 -517.5 271 vss2_dc 8225 -517.5 222 vdd2 4795 -517.5 272 vss2_dc 8295 -517.5 223 vdd2 4865 -517.5 273 dummy 8365 -517.5 224 vdd2 4935 -517.5 274 c6m 8435 -517.5 225 vdd2 5005 -517.5 275 c6m 8505 -517.5 226 vdd2_dc 5075 -517.5 276 c6m 8575 -517.5 227 vdd2_dc 5145 -517.5 277 dummy 8645 -517.5 228 vdd2_dc 5215 -517.5 278 c6p 8715 -517.5 229 vdd2_dc 5285 -517.5 279 c6p 8785 -517.5 230 vdd2_dc 5355 -517.5 280 c6p 8855 -517.5 231 c1m 5425 -517.5 281 dummy 8925 -517.5 232 c1m 5495 -517.5 282 c3m 8995 -517.5 233 c1m 5565 -517.5 283 c3m 9065 -517.5 234 c1m 5635 -517.5 284 c3m 9135 -517.5 235 c1m 5705 -517.5 285 c3p 9205 -517.5 236 c1p 5775 -517.5 286 c3p 9275 -517.5 237 c1p 5845 -517.5 287 c3p 9345 -517.5 238 c1p 5915 -517.5 288 c4m 9415 -517.5 239 c1p 5985 -517.5 289 c4m 9485 -517.5 240 c1p 6055 -517.5 290 c4m 9555 -517.5 241 c2m 6125 -517.5 291 c4p 9625 -517.5 242 c2m 6195 -517.5 292 c4p 9695 -517.5 243 c2m 6265 -517.5 293 c4p 9765 -517.5 244 c2m 6335 -517.5 294 c5m 9835 -517.5 245 c2m 6405 -517.5 295 c5m 9905 -517.5 246 c2p 6475 -517.5 296 c5m 9975 -517.5 247 c2p 6545 -517.5 297 c5p 10045 -517.5 248 c2p 6615 -517.5 298 c5p 10115 -517.5 249 c2p 6685 -517.5 299 c5p 10185 -517.5 250 c2p 6755 -517.5 300 pada<2> 10255 -517.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 201 confidential leadis technology - continued - no name x y no name x y 301 dummy 10325 -517.5 351 g<79> 9790 511.5 302 dummy 10395 -517.5 352 g<81> 9770 386.5 303 dummy 10465 -517.5 353 g<83> 9750 511.5 304 dummy 10745 -517.5 354 g<85> 9730 386.5 305 dummy 10815 -517.5 355 g<87> 9710 511.5 306 dummy 10885 -517.5 356 g<89> 9690 386.5 307 dummy 10670 511.5 357 g<91> 9670 511.5 308 dummy 10650 386.5 358 g<93> 9650 386.5 309 dummy 10630 511.5 359 g<95> 9630 511.5 310 dummy 10610 386.5 360 g<97> 9610 386.5 311 dummy 10590 511.5 361 g<99> 9590 511.5 312 g<1> 10570 386.5 362 g<101> 9570 386.5 313 g<3> 10550 511.5 363 g<103> 9550 511.5 314 g<5> 10530 386.5 364 g<105> 9530 386.5 315 g<7> 10510 511.5 365 g<107> 9510 511.5 316 g<9> 10490 386.5 366 g<109> 9490 386.5 317 g<11> 10470 511.5 367 g<111> 9470 511.5 318 g<13> 10450 386.5 368 g<113> 9450 386.5 319 g<15> 10430 511.5 369 g<115> 9430 511.5 320 g<17> 10410 386.5 370 g<117> 9410 386.5 321 g<19> 10390 511.5 371 g<119> 9390 511.5 322 g<21> 10370 386.5 372 g<121> 9370 386.5 323 g<23> 10350 511.5 373 g<123> 9350 511.5 324 g<25> 10330 386.5 374 g<125> 9330 386.5 325 g<27> 10310 511.5 375 g<127> 9310 511.5 326 g<29> 10290 386.5 376 g<129> 9290 386.5 327 g<31> 10270 511.5 377 g<131> 9270 511.5 328 g<33> 10250 386.5 378 g<133> 9250 386.5 329 g<35> 10230 511.5 379 g<135> 9230 511.5 330 g<37> 10210 386.5 380 g<137> 9210 386.5 331 g<39> 10190 511.5 381 g<139> 9190 511.5 332 g<41> 10170 386.5 382 g<141> 9170 386.5 333 g<43> 10150 511.5 383 g<143> 9150 511.5 334 g<45> 10130 386.5 384 g<145> 9130 386.5 335 g<47> 10110 511.5 385 g<147> 9110 511.5 336 g<49> 10090 386.5 386 g<149> 9090 386.5 337 g<51> 10070 511.5 387 g<151> 9070 511.5 338 g<53> 10050 386.5 388 g<153> 9050 386.5 339 g<55> 10030 511.5 389 g<155> 9030 511.5 340 g<57> 10010 386.5 390 g<157> 9010 386.5 341 g<59> 9990 511.5 391 g<159> 8990 511.5 342 g<61> 9970 386.5 392 g<161> 8970 386.5 343 g<63> 9950 511.5 393 g<163> 8950 511.5 344 g<65> 9930 386.5 394 g<165> 8930 386.5 345 g<67> 9910 511.5 395 g<167> 8910 511.5 346 g<69> 9890 386.5 396 g<169> 8890 386.5 347 g<71> 9870 511.5 397 g<171> 8870 511.5 348 g<73> 9850 386.5 398 g<173> 8850 386.5 349 g<75> 9830 511.5 399 g<175> 8830 511.5 350 g<77> 9810 386.5 400 g<177> 8810 386.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 202 confidential leadis technology - continued - no name x y no name x y 401 g<179> 8790 511.5 451 g<279> 7790 511.5 402 g<181> 8770 386.5 452 g<281> 7770 386.5 403 g<183> 8750 511.5 453 g<283> 7750 511.5 404 g<185> 8730 386.5 454 g<285> 7730 386.5 405 g<187> 8710 511.5 455 g<287> 7710 511.5 406 g<189> 8690 386.5 456 g<289> 7690 386.5 407 g<191> 8670 511.5 457 g<291> 7670 511.5 408 g<193> 8650 386.5 458 g<293> 7650 386.5 409 g<195> 8630 511.5 459 g<295> 7630 511.5 410 g<197> 8610 386.5 460 g<297> 7610 386.5 411 g<199> 8590 511.5 461 g<299> 7590 511.5 412 g<201> 8570 386.5 462 g<301> 7570 386.5 413 g<203> 8550 511.5 463 g<303> 7550 511.5 414 g<205> 8530 386.5 464 g<305> 7530 386.5 415 g<207> 8510 511.5 465 g<307> 7510 511.5 416 g<209> 8490 386.5 466 g<309> 7490 386.5 417 g<211> 8470 511.5 467 g<311> 7470 511.5 418 g<213> 8450 386.5 468 g<313> 7450 386.5 419 g<215> 8430 511.5 469 g<315> 7430 511.5 420 g<217> 8410 386.5 470 g<317> 7410 386.5 421 g<219> 8390 511.5 471 g<319> 7390 511.5 422 g<221> 8370 386.5 472 dummy 7370 386.5 423 g<223> 8350 511.5 473 dummy 7350 511.5 424 g<225> 8330 386.5 474 dummy 7130 511.5 425 g<227> 8310 511.5 475 s<720> 7110 386.5 426 g<229> 8290 386.5 476 s<719> 7090 511.5 427 g<231> 8270 511.5 477 s<718> 7070 386.5 428 g<233> 8250 386.5 478 s<717> 7050 511.5 429 g<235> 8230 511.5 479 s<716> 7030 386.5 430 g<237> 8210 386.5 480 s<715> 7010 511.5 431 g<239> 8190 511.5 481 s<714> 6990 386.5 432 g<241> 8170 386.5 482 s<713> 6970 511.5 433 g<243> 8150 511.5 483 s<712> 6950 386.5 434 g<245> 8130 386.5 484 s<711> 6930 511.5 435 g<247> 8110 511.5 485 s<710> 6910 386.5 436 g<249> 8090 386.5 486 s<709> 6890 511.5 437 g<251> 8070 511.5 487 s<708> 6870 386.5 438 g<253> 8050 386.5 488 s<707> 6850 511.5 439 g<255> 8030 511.5 489 s<706> 6830 386.5 440 g<257> 8010 386.5 490 s<705> 6810 511.5 441 g<259> 7990 511.5 491 s<704> 6790 386.5 442 g<261> 7970 386.5 492 s<703> 6770 511.5 443 g<263> 7950 511.5 493 s<702> 6750 386.5 444 g<265> 7930 386.5 494 s<701> 6730 511.5 445 g<267> 7910 511.5 495 s<700> 6710 386.5 446 g<269> 7890 386.5 496 s<699> 6690 511.5 447 g<271> 7870 511.5 497 s<698> 6670 386.5 448 g<273> 7850 386.5 498 s<697> 6650 511.5 449 g<275> 7830 511.5 499 s<696> 6630 386.5 450 g<277> 7810 386.5 500 s<695> 6610 511.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 203 confidential leadis technology - continued - no name x y no name x y 501 s<694> 6590 386.5 551 s<644> 5590 386.5 502 s<693> 6570 511.5 552 s<643> 5570 511.5 503 s<692> 6550 386.5 553 s<642> 5550 386.5 504 s<691> 6530 511.5 554 s<641> 5530 511.5 505 s<690> 6510 386.5 555 s<640> 5510 386.5 506 s<689> 6490 511.5 556 s<639> 5490 511.5 507 s<688> 6470 386.5 557 s<638> 5470 386.5 508 s<687> 6450 511.5 558 s<637> 5450 511.5 509 s<686> 6430 386.5 559 s<636> 5430 386.5 510 s<685> 6410 511.5 560 s<635> 5410 511.5 511 s<684> 6390 386.5 561 s<634> 5390 386.5 512 s<683> 6370 511.5 562 s<633> 5370 511.5 513 s<682> 6350 386.5 563 s<632> 5350 386.5 514 s<681> 6330 511.5 564 s<631> 5330 511.5 515 s<680> 6310 386.5 565 s<630> 5310 386.5 516 s<679> 6290 511.5 566 s<629> 5290 511.5 517 s<678> 6270 386.5 567 s<628> 5270 386.5 518 s<677> 6250 511.5 568 s<627> 5250 511.5 519 s<676> 6230 386.5 569 s<626> 5230 386.5 520 s<675> 6210 511.5 570 s<625> 5210 511.5 521 s<674> 6190 386.5 571 s<624> 5190 386.5 522 s<673> 6170 511.5 572 s<623> 5170 511.5 523 s<672> 6150 386.5 573 s<622> 5150 386.5 524 s<671> 6130 511.5 574 s<621> 5130 511.5 525 s<670> 6110 386.5 575 s<620> 5110 386.5 526 s<669> 6090 511.5 576 s<619> 5090 511.5 527 s<668> 6070 386.5 577 s<618> 5070 386.5 528 s<667> 6050 511.5 578 s<617> 5050 511.5 529 s<666> 6030 386.5 579 s<616> 5030 386.5 530 s<665> 6010 511.5 580 s<615> 5010 511.5 531 s<664> 5990 386.5 581 s<614> 4990 386.5 532 s<663> 5970 511.5 582 s<613> 4970 511.5 533 s<662> 5950 386.5 583 s<612> 4950 386.5 534 s<661> 5930 511.5 584 s<611> 4930 511.5 535 s<660> 5910 386.5 585 s<610> 4910 386.5 536 s<659> 5890 511.5 586 s<609> 4890 511.5 537 s<658> 5870 386.5 587 s<608> 4870 386.5 538 s<657> 5850 511.5 588 s<607> 4850 511.5 539 s<656> 5830 386.5 589 s<606> 4830 386.5 540 s<655> 5810 511.5 590 s<605> 4810 511.5 541 s<654> 5790 386.5 591 s<604> 4790 386.5 542 s<653> 5770 511.5 592 s<603> 4770 511.5 543 s<652> 5750 386.5 593 s<602> 4750 386.5 544 s<651> 5730 511.5 594 s<601> 4730 511.5 545 s<650> 5710 386.5 595 s<600> 4710 386.5 546 s<649> 5690 511.5 596 s<599> 4690 511.5 547 s<648> 5670 386.5 597 s<598> 4670 386.5 548 s<647> 5650 511.5 598 s<597> 4650 511.5 549 s<646> 5630 386.5 599 s<596> 4630 386.5 550 s<645> 5610 511.5 600 s<595> 4610 511.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 204 confidential leadis technology - continued - no name x y no name x y 601 s<594> 4590 386.5 651 s<544> 3590 386.5 602 s<593> 4570 511.5 652 s<543> 3570 511.5 603 s<592> 4550 386.5 653 s<542> 3550 386.5 604 s<591> 4530 511.5 654 s<541> 3530 511.5 605 s<590> 4510 386.5 655 s<540> 3510 386.5 606 s<589> 4490 511.5 656 s<539> 3490 511.5 607 s<588> 4470 386.5 657 s<538> 3470 386.5 608 s<587> 4450 511.5 658 s<537> 3450 511.5 609 s<586> 4430 386.5 659 s<536> 3430 386.5 610 s<585> 4410 511.5 660 s<535> 3410 511.5 611 s<584> 4390 386.5 661 s<534> 3390 386.5 612 s<583> 4370 511.5 662 s<533> 3370 511.5 613 s<582> 4350 386.5 663 s<532> 3350 386.5 614 s<581> 4330 511.5 664 s<531> 3330 511.5 615 s<580> 4310 386.5 665 s<530> 3310 386.5 616 s<579> 4290 511.5 666 s<529> 3290 511.5 617 s<578> 4270 386.5 667 s<528> 3270 386.5 618 s<577> 4250 511.5 668 s<527> 3250 511.5 619 s<576> 4230 386.5 669 s<526> 3230 386.5 620 s<575> 4210 511.5 670 s<525> 3210 511.5 621 s<574> 4190 386.5 671 s<524> 3190 386.5 622 s<573> 4170 511.5 672 s<523> 3170 511.5 623 s<572> 4150 386.5 673 s<522> 3150 386.5 624 s<571> 4130 511.5 674 s<521> 3130 511.5 625 s<570> 4110 386.5 675 s<520> 3110 386.5 626 s<569> 4090 511.5 676 s<519> 3090 511.5 627 s<568> 4070 386.5 677 s<518> 3070 386.5 628 s<567> 4050 511.5 678 s<517> 3050 511.5 629 s<566> 4030 386.5 679 s<516> 3030 386.5 630 s<565> 4010 511.5 680 s<515> 3010 511.5 631 s<564> 3990 386.5 681 s<514> 2990 386.5 632 s<563> 3970 511.5 682 s<513> 2970 511.5 633 s<562> 3950 386.5 683 s<512> 2950 386.5 634 s<561> 3930 511.5 684 s<511> 2930 511.5 635 s<560> 3910 386.5 685 s<510> 2910 386.5 636 s<559> 3890 511.5 686 s<509> 2890 511.5 637 s<558> 3870 386.5 687 s<508> 2870 386.5 638 s<557> 3850 511.5 688 s<507> 2850 511.5 639 s<556> 3830 386.5 689 s<506> 2830 386.5 640 s<555> 3810 511.5 690 s<505> 2810 511.5 641 s<554> 3790 386.5 691 s<504> 2790 386.5 642 s<553> 3770 511.5 692 s<503> 2770 511.5 643 s<552> 3750 386.5 693 s<502> 2750 386.5 644 s<551> 3730 511.5 694 s<501> 2730 511.5 645 s<550> 3710 386.5 695 s<500> 2710 386.5 646 s<549> 3690 511.5 696 s<499> 2690 511.5 647 s<548> 3670 386.5 697 s<498> 2670 386.5 648 s<547> 3650 511.5 698 s<497> 2650 511.5 649 s<546> 3630 386.5 699 s<496> 2630 386.5 650 s<545> 3610 511.5 700 s<495> 2610 511.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 205 confidential leadis technology - continued - no name x y no name x y 701 s<494> 2590 386.5 751 s<444> 1590 386.5 702 s<493> 2570 511.5 752 s<443> 1570 511.5 703 s<492> 2550 386.5 753 s<442> 1550 386.5 704 s<491> 2530 511.5 754 s<441> 1530 511.5 705 s<490> 2510 386.5 755 s<440> 1510 386.5 706 s<489> 2490 511.5 756 s<439> 1490 511.5 707 s<488> 2470 386.5 757 s<438> 1470 386.5 708 s<487> 2450 511.5 758 s<437> 1450 511.5 709 s<486> 2430 386.5 759 s<436> 1430 386.5 710 s<485> 2410 511.5 760 s<435> 1410 511.5 711 s<484> 2390 386.5 761 s<434> 1390 386.5 712 s<483> 2370 511.5 762 s<433> 1370 511.5 713 s<482> 2350 386.5 763 s<432> 1350 386.5 714 s<481> 2330 511.5 764 s<431> 1330 511.5 715 s<480> 2310 386.5 765 s<430> 1310 386.5 716 s<479> 2290 511.5 766 s<429> 1290 511.5 717 s<478> 2270 386.5 767 s<428> 1270 386.5 718 s<477> 2250 511.5 768 s<427> 1250 511.5 719 s<476> 2230 386.5 769 s<426> 1230 386.5 720 s<475> 2210 511.5 770 s<425> 1210 511.5 721 s<474> 2190 386.5 771 s<424> 1190 386.5 722 s<473> 2170 511.5 772 s<423> 1170 511.5 723 s<472> 2150 386.5 773 s<422> 1150 386.5 724 s<471> 2130 511.5 774 s<421> 1130 511.5 725 s<470> 2110 386.5 775 s<420> 1110 386.5 726 s<469> 2090 511.5 776 s<419> 1090 511.5 727 s<468> 2070 386.5 777 s<418> 1070 386.5 728 s<467> 2050 511.5 778 s<417> 1050 511.5 729 s<466> 2030 386.5 779 s<416> 1030 386.5 730 s<465> 2010 511.5 780 s<415> 1010 511.5 731 s<464> 1990 386.5 781 s<414> 990 386.5 732 s<463> 1970 511.5 782 s<413> 970 511.5 733 s<462> 1950 386.5 783 s<412> 950 386.5 734 s<461> 1930 511.5 784 s<411> 930 511.5 735 s<460> 1910 386.5 785 s<410> 910 386.5 736 s<459> 1890 511.5 786 s<409> 890 511.5 737 s<458> 1870 386.5 787 s<408> 870 386.5 738 s<457> 1850 511.5 788 s<407> 850 511.5 739 s<456> 1830 386.5 789 s<406> 830 386.5 740 s<455> 1810 511.5 790 s<405> 810 511.5 741 s<454> 1790 386.5 791 s<404> 790 386.5 742 s<453> 1770 511.5 792 s<403> 770 511.5 743 s<452> 1750 386.5 793 s<402> 750 386.5 744 s<451> 1730 511.5 794 s<401> 730 511.5 745 s<450> 1710 386.5 795 s<400> 710 386.5 746 s<449> 1690 511.5 796 s<399> 690 511.5 747 s<448> 1670 386.5 797 s<398> 670 386.5 748 s<447> 1650 511.5 798 s<397> 650 511.5 749 s<446> 1630 386.5 799 s<396> 630 386.5 750 s<445> 1610 511.5 800 s<395> 610 511.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 206 confidential leadis technology - continued - no name x y no name x y 801 s<394> 590 386.5 851 s<344> -410 386.5 802 s<393> 570 511.5 852 s<343> -430 511.5 803 s<392> 550 386.5 853 s<342> -450 386.5 804 s<391> 530 511.5 854 s<341> -470 511.5 805 s<390> 510 386.5 855 s<340> -490 386.5 806 s<389> 490 511.5 856 s<339> -510 511.5 807 s<388> 470 386.5 857 s<338> -530 386.5 808 s<387> 450 511.5 858 s<337> -550 511.5 809 s<386> 430 386.5 859 s<336> -570 386.5 810 s<385> 410 511.5 860 s<335> -590 511.5 811 s<384> 390 386.5 861 s<334> -610 386.5 812 s<383> 370 511.5 862 s<333> -630 511.5 813 s<382> 350 386.5 863 s<332> -650 386.5 814 s<381> 330 511.5 864 s<331> -670 511.5 815 s<380> 310 386.5 865 s<330> -690 386.5 816 s<379> 290 511.5 866 s<329> -710 511.5 817 s<378> 270 386.5 867 s<328> -730 386.5 818 s<377> 250 511.5 868 s<327> -750 511.5 819 s<376> 230 386.5 869 s<326> -770 386.5 820 s<375> 210 511.5 870 s<325> -790 511.5 821 s<374> 190 386.5 871 s<324> -810 386.5 822 s<373> 170 511.5 872 s<323> -830 511.5 823 s<372> 150 386.5 873 s<322> -850 386.5 824 s<371> 130 511.5 874 s<321> -870 511.5 825 s<370> 110 386.5 875 s<320> -890 386.5 826 s<369> 90 511.5 876 s<319> -910 511.5 827 s<368> 70 386.5 877 s<318> -930 386.5 828 s<367> 50 511.5 878 s<317> -950 511.5 829 s<366> 30 386.5 879 s<316> -970 386.5 830 s<365> 10 511.5 880 s<315> -990 511.5 831 s<364> -10 386.5 881 s<314> -1010 386.5 832 s<363> -30 511.5 882 s<313> -1030 511.5 833 s<362> -50 386.5 883 s<312> -1050 386.5 834 s<361> -70 511.5 884 s<311> -1070 511.5 835 s<360> -90 386.5 885 s<310> -1090 386.5 836 s<359> -110 511.5 886 s<309> -1110 511.5 837 s<358> -130 386.5 887 s<308> -1130 386.5 838 s<357> -150 511.5 888 s<307> -1150 511.5 839 s<356> -170 386.5 889 s<306> -1170 386.5 840 s<355> -190 511.5 890 s<305> -1190 511.5 841 s<354> -210 386.5 891 s<304> -1210 386.5 842 s<353> -230 511.5 892 s<303> -1230 511.5 843 s<352> -250 386.5 893 s<302> -1250 386.5 844 s<351> -270 511.5 894 s<301> -1270 511.5 845 s<350> -290 386.5 895 s<300> -1290 386.5 846 s<349> -310 511.5 896 s<299> -1310 511.5 847 s<348> -330 386.5 897 s<298> -1330 386.5 848 s<347> -350 511.5 898 s<297> -1350 511.5 849 s<346> -370 386.5 899 s<296> -1370 386.5 850 s<345> -390 511.5 900 s<295> -1390 511.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 207 confidential leadis technology - continued - no name x y no name x y 901 s<294> -1410 386.5 951 s<244> -2410 386.5 902 s<293> -1430 511.5 952 s<243> -2430 511.5 903 s<292> -1450 386.5 953 s<242> -2450 386.5 904 s<291> -1470 511.5 954 s<241> -2470 511.5 905 s<290> -1490 386.5 955 s<240> -2490 386.5 906 s<289> -1510 511.5 956 s<239> -2510 511.5 907 s<288> -1530 386.5 957 s<238> -2530 386.5 908 s<287> -1550 511.5 958 s<237> -2550 511.5 909 s<286> -1570 386.5 959 s<236> -2570 386.5 910 s<285> -1590 511.5 960 s<235> -2590 511.5 911 s<284> -1610 386.5 961 s<234> -2610 386.5 912 s<283> -1630 511.5 962 s<233> -2630 511.5 913 s<282> -1650 386.5 963 s<232> -2650 386.5 914 s<281> -1670 511.5 964 s<231> -2670 511.5 915 s<280> -1690 386.5 965 s<230> -2690 386.5 916 s<279> -1710 511.5 966 s<229> -2710 511.5 917 s<278> -1730 386.5 967 s<228> -2730 386.5 918 s<277> -1750 511.5 968 s<227> -2750 511.5 919 s<276> -1770 386.5 969 s<226> -2770 386.5 920 s<275> -1790 511.5 970 s<225> -2790 511.5 921 s<274> -1810 386.5 971 s<224> -2810 386.5 922 s<273> -1830 511.5 972 s<223> -2830 511.5 923 s<272> -1850 386.5 973 s<222> -2850 386.5 924 s<271> -1870 511.5 974 s<221> -2870 511.5 925 s<270> -1890 386.5 975 s<220> -2890 386.5 926 s<269> -1910 511.5 976 s<219> -2910 511.5 927 s<268> -1930 386.5 977 s<218> -2930 386.5 928 s<267> -1950 511.5 978 s<217> -2950 511.5 929 s<266> -1970 386.5 979 s<216> -2970 386.5 930 s<265> -1990 511.5 980 s<215> -2990 511.5 931 s<264> -2010 386.5 981 s<214> -3010 386.5 932 s<263> -2030 511.5 982 s<213> -3030 511.5 933 s<262> -2050 386.5 983 s<212> -3050 386.5 934 s<261> -2070 511.5 984 s<211> -3070 511.5 935 s<260> -2090 386.5 985 s<210> -3090 386.5 936 s<259> -2110 511.5 986 s<209> -3110 511.5 937 s<258> -2130 386.5 987 s<208> -3130 386.5 938 s<257> -2150 511.5 988 s<207> -3150 511.5 939 s<256> -2170 386.5 989 s<206> -3170 386.5 940 s<255> -2190 511.5 990 s<205> -3190 511.5 941 s<254> -2210 386.5 991 s<204> -3210 386.5 942 s<253> -2230 511.5 992 s<203> -3230 511.5 943 s<252> -2250 386.5 993 s<202> -3250 386.5 944 s<251> -2270 511.5 994 s<201> -3270 511.5 945 s<250> -2290 386.5 995 s<200> -3290 386.5 946 s<249> -2310 511.5 996 s<199> -3310 511.5 947 s<248> -2330 386.5 997 s<198> -3330 386.5 948 s<247> -2350 511.5 998 s<197> -3350 511.5 949 s<246> -2370 386.5 999 s<196> -3370 386.5 950 s<245> -2390 511.5 1000 s<195> -3390 511.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 208 confidential leadis technology - continued - no name x y no name x y 1001 s<194> -3410 386.5 1051 s<144> -4410 386.5 1002 s<193> -3430 511.5 1052 s<143> -4430 511.5 1003 s<192> -3450 386.5 1053 s<142> -4450 386.5 1004 s<191> -3470 511.5 1054 s<141> -4470 511.5 1005 s<190> -3490 386.5 1055 s<140> -4490 386.5 1006 s<189> -3510 511.5 1056 s<139> -4510 511.5 1007 s<188> -3530 386.5 1057 s<138> -4530 386.5 1008 s<187> -3550 511.5 1058 s<137> -4550 511.5 1009 s<186> -3570 386.5 1059 s<136> -4570 386.5 1010 s<185> -3590 511.5 1060 s<135> -4590 511.5 1011 s<184> -3610 386.5 1061 s<134> -4610 386.5 1012 s<183> -3630 511.5 1062 s<133> -4630 511.5 1013 s<182> -3650 386.5 1063 s<132> -4650 386.5 1014 s<181> -3670 511.5 1064 s<131> -4670 511.5 1015 s<180> -3690 386.5 1065 s<130> -4690 386.5 1016 s<179> -3710 511.5 1066 s<129> -4710 511.5 1017 s<178> -3730 386.5 1067 s<128> -4730 386.5 1018 s<177> -3750 511.5 1068 s<127> -4750 511.5 1019 s<176> -3770 386.5 1069 s<126> -4770 386.5 1020 s<175> -3790 511.5 1070 s<125> -4790 511.5 1021 s<174> -3810 386.5 1071 s<124> -4810 386.5 1022 s<173> -3830 511.5 1072 s<123> -4830 511.5 1023 s<172> -3850 386.5 1073 s<122> -4850 386.5 1024 s<171> -3870 511.5 1074 s<121> -4870 511.5 1025 s<170> -3890 386.5 1075 s<120> -4890 386.5 1026 s<169> -3910 511.5 1076 s<119> -4910 511.5 1027 s<168> -3930 386.5 1077 s<118> -4930 386.5 1028 s<167> -3950 511.5 1078 s<117> -4950 511.5 1029 s<166> -3970 386.5 1079 s<116> -4970 386.5 1030 s<165> -3990 511.5 1080 s<115> -4990 511.5 1031 s<164> -4010 386.5 1081 s<114> -5010 386.5 1032 s<163> -4030 511.5 1082 s<113> -5030 511.5 1033 s<162> -4050 386.5 1083 s<112> -5050 386.5 1034 s<161> -4070 511.5 1084 s<111> -5070 511.5 1035 s<160> -4090 386.5 1085 s<110> -5090 386.5 1036 s<159> -4110 511.5 1086 s<109> -5110 511.5 1037 s<158> -4130 386.5 1087 s<108> -5130 386.5 1038 s<157> -4150 511.5 1088 s<107> -5150 511.5 1039 s<156> -4170 386.5 1089 s<106> -5170 386.5 1040 s<155> -4190 511.5 1090 s<105> -5190 511.5 1041 s<154> -4210 386.5 1091 s<104> -5210 386.5 1042 s<153> -4230 511.5 1092 s<103> -5230 511.5 1043 s<152> -4250 386.5 1093 s<102> -5250 386.5 1044 s<151> -4270 511.5 1094 s<101> -5270 511.5 1045 s<150> -4290 386.5 1095 s<100> -5290 386.5 1046 s<149> -4310 511.5 1096 s<99> -5310 511.5 1047 s<148> -4330 386.5 1097 s<98> -5330 386.5 1048 s<147> -4350 511.5 1098 s<97> -5350 511.5 1049 s<146> -4370 386.5 1099 s<96> -5370 386.5 1050 s<145> -4390 511.5 1100 s<95> -5390 511.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 209 confidential leadis technology - continued - no name x y no name x y 1101 s<94> -5410 386.5 1151 s<44> -6410 386.5 1102 s<93> -5430 511.5 1152 s<43> -6430 511.5 1103 s<92> -5450 386.5 1153 s<42> -6450 386.5 1104 s<91> -5470 511.5 1154 s<41> -6470 511.5 1105 s<90> -5490 386.5 1155 s<40> -6490 386.5 1106 s<89> -5510 511.5 1156 s<39> -6510 511.5 1107 s<88> -5530 386.5 1157 s<38> -6530 386.5 1108 s<87> -5550 511.5 1158 s<37> -6550 511.5 1109 s<86> -5570 386.5 1159 s<36> -6570 386.5 1110 s<85> -5590 511.5 1160 s<35> -6590 511.5 1111 s<84> -5610 386.5 1161 s<34> -6610 386.5 1112 s<83> -5630 511.5 1162 s<33> -6630 511.5 1113 s<82> -5650 386.5 1163 s<32> -6650 386.5 1114 s<81> -5670 511.5 1164 s<31> -6670 511.5 1115 s<80> -5690 386.5 1165 s<30> -6690 386.5 1116 s<79> -5710 511.5 1166 s<29> -6710 511.5 1117 s<78> -5730 386.5 1167 s<28> -6730 386.5 1118 s<77> -5750 511.5 1168 s<27> -6750 511.5 1119 s<76> -5770 386.5 1169 s<26> -6770 386.5 1120 s<75> -5790 511.5 1170 s<25> -6790 511.5 1121 s<74> -5810 386.5 1171 s<24> -6810 386.5 1122 s<73> -5830 511.5 1172 s<23> -6830 511.5 1123 s<72> -5850 386.5 1173 s<22> -6850 386.5 1124 s<71> -5870 511.5 1174 s<21> -6870 511.5 1125 s<70> -5890 386.5 1175 s<20> -6890 386.5 1126 s<69> -5910 511.5 1176 s<19> -6910 511.5 1127 s<68> -5930 386.5 1177 s<18> -6930 386.5 1128 s<67> -5950 511.5 1178 s<17> -6950 511.5 1129 s<66> -5970 386.5 1179 s<16> -6970 386.5 1130 s<65> -5990 511.5 1180 s<15> -6990 511.5 1131 s<64> -6010 386.5 1181 s<14> -7010 386.5 1132 s<63> -6030 511.5 1182 s<13> -7030 511.5 1133 s<62> -6050 386.5 1183 s<12> -7050 386.5 1134 s<61> -6070 511.5 1184 s<11> -7070 511.5 1135 s<60> -6090 386.5 1185 s<10> -7090 386.5 1136 s<59> -6110 511.5 1186 s<9> -7110 511.5 1137 s<58> -6130 386.5 1187 s<8> -7130 386.5 1138 s<57> -6150 511.5 1188 s<7> -7150 511.5 1139 s<56> -6170 386.5 1189 s<6> -7170 386.5 1140 s<55> -6190 511.5 1190 s<5> -7190 511.5 1141 s<54> -6210 386.5 1191 s<4> -7210 386.5 1142 s<53> -6230 511.5 1192 s<3> -7230 511.5 1143 s<52> -6250 386.5 1193 s<2> -7250 386.5 1144 s<51> -6270 511.5 1194 s<1> -7270 511.5 1145 s<50> -6290 386.5 1195 dummy -7290 386.5 1146 s<49> -6310 511.5 1196 dummy -7350 511.5 1147 s<48> -6330 386.5 1197 dummy -7370 386.5 1148 s<47> -6350 511.5 1198 g<320> -7390 511.5 1149 s<46> -6370 386.5 1199 g<318> -7410 386.5 1150 s<45> -6390 511.5 1200 g<316> -7430 511.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 210 confidential leadis technology - continued - no name x y no name x y 1201 g<314> -7450 386.5 1251 g<214> -8450 386.5 1202 g<312> -7470 511.5 1252 g<212> -8470 511.5 1203 g<310> -7490 386.5 1253 g<210> -8490 386.5 1204 g<308> -7510 511.5 1254 g<208> -8510 511.5 1205 g<306> -7530 386.5 1255 g<206> -8530 386.5 1206 g<304> -7550 511.5 1256 g<204> -8550 511.5 1207 g<302> -7570 386.5 1257 g<202> -8570 386.5 1208 g<300> -7590 511.5 1258 g<200> -8590 511.5 1209 g<298> -7610 386.5 1259 g<198> -8610 386.5 1210 g<296> -7630 511.5 1260 g<196> -8630 511.5 1211 g<294> -7650 386.5 1261 g<194> -8650 386.5 1212 g<292> -7670 511.5 1262 g<192> -8670 511.5 1213 g<290> -7690 386.5 1263 g<190> -8690 386.5 1214 g<288> -7710 511.5 1264 g<188> -8710 511.5 1215 g<286> -7730 386.5 1265 g<186> -8730 386.5 1216 g<284> -7750 511.5 1266 g<184> -8750 511.5 1217 g<282> -7770 386.5 1267 g<182> -8770 386.5 1218 g<280> -7790 511.5 1268 g<180> -8790 511.5 1219 g<278> -7810 386.5 1269 g<178> -8810 386.5 1220 g<276> -7830 511.5 1270 g<176> -8830 511.5 1221 g<274> -7850 386.5 1271 g<174> -8850 386.5 1222 g<272> -7870 511.5 1272 g<172> -8870 511.5 1223 g<270> -7890 386.5 1273 g<170> -8890 386.5 1224 g<268> -7910 511.5 1274 g<168> -8910 511.5 1225 g<266> -7930 386.5 1275 g<166> -8930 386.5 1226 g<264> -7950 511.5 1276 g<164> -8950 511.5 1227 g<262> -7970 386.5 1277 g<162> -8970 386.5 1228 g<260> -7990 511.5 1278 g<160> -8990 511.5 1229 g<258> -8010 386.5 1279 g<158> -9010 386.5 1230 g<256> -8030 511.5 1280 g<156> -9030 511.5 1231 g<254> -8050 386.5 1281 g<154> -9050 386.5 1232 g<252> -8070 511.5 1282 g<152> -9070 511.5 1233 g<250> -8090 386.5 1283 g<150> -9090 386.5 1234 g<248> -8110 511.5 1284 g<148> -9110 511.5 1235 g<246> -8130 386.5 1285 g<146> -9130 386.5 1236 g<244> -8150 511.5 1286 g<144> -9150 511.5 1237 g<242> -8170 386.5 1287 g<142> -9170 386.5 1238 g<240> -8190 511.5 1288 g<140> -9190 511.5 1239 g<238> -8210 386.5 1289 g<138> -9210 386.5 1240 g<236> -8230 511.5 1290 g<136> -9230 511.5 1241 g<234> -8250 386.5 1291 g<134> -9250 386.5 1242 g<232> -8270 511.5 1292 g<132> -9270 511.5 1243 g<230> -8290 386.5 1293 g<130> -9290 386.5 1244 g<228> -8310 511.5 1294 g<128> -9310 511.5 1245 g<226> -8330 386.5 1295 g<126> -9330 386.5 1246 g<224> -8350 511.5 1296 g<124> -9350 511.5 1247 g<222> -8370 386.5 1297 g<122> -9370 386.5 1248 g<220> -8390 511.5 1298 g<120> -9390 511.5 1249 g<218> -8410 386.5 1299 g<118> -9410 386.5 1250 g<216> -8430 511.5 1300 g<116> -9430 511.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 211 confidential leadis technology - continued - no name x y no name x y 1301 g<114> -9450 386.5 1351 g<14> -10450 386.5 1302 g<112> -9470 511.5 1352 g<12> -10470 511.5 1303 g<110> -9490 386.5 1353 g<10> -10490 386.5 1304 g<108> -9510 511.5 1354 g<8> -10510 511.5 1305 g<106> -9530 386.5 1355 g<6> -10530 386.5 1306 g<104> -9550 511.5 1356 g<4> -10550 511.5 1307 g<102> -9570 386.5 1357 g<2> -10570 386.5 1308 g<100> -9590 511.5 1358 dummy -10590 511.5 1309 g<98> -9610 386.5 1359 dummy -10610 386.5 1310 g<96> -9630 511.5 1360 dummy -10630 511.5 1311 g<94> -9650 386.5 1361 dummy -10650 386.5 1312 g<92> -9670 511.5 1362 dummy -10670 511.5 1313 g<90> -9690 386.5 1314 g<88> -9710 511.5 key_cog -10613 -468 1315 g<86> -9730 386.5 key_cog 10613 -468 1316 g<84> -9750 511.5 1317 g<82> -9770 386.5 1318 g<80> -9790 511.5 1319 g<78> -9810 386.5 1320 g<76> -9830 511.5 1321 g<74> -9850 386.5 1322 g<72> -9870 511.5 1323 g<70> -9890 386.5 1324 g<68> -9910 511.5 1325 g<66> -9930 386.5 1326 g<64> -9950 511.5 1327 g<62> -9970 386.5 1328 g<60> -9990 511.5 1329 g<58> -10010 386.5 1330 g<56> -10030 511.5 1331 g<54> -10050 386.5 1332 g<52> -10070 511.5 1333 g<50> -10090 386.5 1334 g<48> -10110 511.5 1335 g<46> -10130 386.5 1336 g<44> -10150 511.5 1337 g<42> -10170 386.5 1338 g<40> -10190 511.5 1339 g<38> -10210 386.5 1340 g<36> -10230 511.5 1341 g<34> -10250 386.5 1342 g<32> -10270 511.5 1343 g<30> -10290 386.5 1344 g<28> -10310 511.5 1345 g<26> -10330 386.5 1346 g<24> -10350 511.5 1347 g<22> -10370 386.5 1348 g<20> -10390 511.5 1349 g<18> -10410 386.5 1350 g<16> -10430 511.5 www.datasheet.co.kr datasheet pdf - http://www..net/
240 (rgb) x 320 16m-color tft driver LDS285 version 2.00 212 confidential leadis technology product notice no part of this document may be copied or reproduced in any fo rm without the prior written cons ent of leadis technology, inc. leadis makes no representations or warranties with respect to th e accuracy or completeness of the contents of this document. leadis? specifications and product descriptions are subject to chan ge at any time without notice due to product improvements or other reasons. as a result, we recommend that customers contact leadis for the late st product information before purchasing or using any leadis product. these materials are intended as a reference to assist our cust omers in the selection and application of leadis products. these materials do not convey any license (express, implied or otherw ise) under any intellectual proper ty rights of leadis or others. leadis assumes no responsibility for any infringement of patents or other rights of third parties that may result from the use of these materials. except as set forth in leadis? standard terms and conditions of sale, leadis assumes no liability, and disclaims any express or implied warranty, relating to its products , including, but not limited to, any impli ed warranties of merchantability, fitness f or a particular purpose or noninfringem ent. leadis? products have not been designed, tested or manufactured for use in applications where the failure, malfunction or inaccuracy of the products carr ies a risk of death or serious bodily injury or damage to tang ible property, including, but not limited to, nuclear facilities, aircraft navigation or communication, emergency systems, or other applications with a similar degree of potential hazard. please contact leadis for further details on thes e materials or the products described herein. ? 2007 leadis technology, inc. all rights reserved. leadis and the leadis logo are trademarks of leadis technology, inc. www.datasheet.co.kr datasheet pdf - http://www..net/

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